A dynamic semiconductor memory device

Claim 2

A dynamic semiconductor memory device comprising a one-transistor one-capacitor dynamic memory cell, a word line (WL 10 ), a bit line (BL 10 ), and a voltage dividing circuit (R 10 ,R 20 ) having a potential-providing terminal for providing an intermediate potential between a power supply potential and a ground potential; the single transistor (Q l ) of the cell having a gate electrode connected to the word line and having two other electrodes; the single capacitor (C 1 ) of the cell having a first electrode, which is connected to one of the said other electrodes of the transistor, and an opposite electrode which is operatively connected to the potential-providing terminal (N 20 ) of the voltage-dividing circuit; characterized in that the voltage-dividing circuit comprises a potential switching circuit (R 30 ,Q 2 ) for changing the intermediate potential synchronously with the operation of the memory device.

Claim 3

A dynamic semiconductor memory device as set forth in claim 1 or 2, wherein the potential-switching circuit in the voltage-dividing circuit operatively changes the intermediate potential in conformity with changes of the potential at the said opposite electrode of the capacitor (C 1 ).

Claim 4

A dynamic semiconductor memory device as set forth in claim 1 or 2, wherein the potential-switching circuit is driven by an internal clock signal(φ A ) obtained from a row address strobe signal (RAS) for providing alternate sequences of an active interval and a reset interval of the memory device.

Claim 5

A dynamic semiconductor memory device as set forth in claim 1, 2 or 3, wherein the potential-switching circuit in the voltage-dividing circuit operatively provides a first potential higher than the half of the power supply potential by a first predetermined value during at least a part of each of the reset intervals, and operatively provides a second potential lower than the half of the power supply potential by a second predetermined value during at least a part of each of the active intervals.

Claim 6

A dynamic semiconductor memory device as set fortn in claim 1, 2, 3 or 4, wherein the voltage-dividing circuit comprises a first resistor (R 10 ) and a second resistor (R 20 ) connected in series between a power supply line (V cc ) and a ground line (V SS ), the potential-switching circuit in the voltage-dividing circuit comprises a third resistor (R 30 ) and a switching transistor (Q 2 ) having a control electrode for turning on or off the switching transistor, to switch the intermediate potential at the potential-providing terminal from the first potential to the second potential and having two other electrodes, one end of the third resistor being connected to a connecting point between the first resistor and the second resistor, the other end of the third resistor being connected to one of the two other electrodes of the switching transistor,the other of the two other electrodes of the switching transistor being connected to the ground line, the Iconnecting point being connected to the potential-providing terminal.

Claim 7

A dynamic semiconductor memory device as set forth in claim 5, wherein the resistance values of the first resistor, the second resistor,and the third resistor are so determined that the change of the potential at the potential-providing terminal is equal to the change of the potential at the second electrode of the capacitor which is generated by the operation of the memory device.

Claim 8

A dynamic semiconductor memory device as set forth in claim 5 or 6, wherein the resistance value of the first resistance (R 10 ) is smaller than the resistance value of the second resistor (R 20 ), and the resistance value of the second resistor (R 20 ) and the third resistor (R30) when connected in parallel is smaller than the resistance value of the first resistor.

Claim 9

A dynamic semiconductor memory device as set forth in any one of claims 1 to 4, wherein the voltage-dividing circuit comprises a first resistor (R 10 ) and a second resistor (R20) connected in series between a power supply line and a ground line, a third resistor (R 31 ) and a fourth resistor (R 41 ) connected in series between the power supply line and the ground line, a first switching transistor (Q 3 ) having a first control electrode for turning on or off the first switching transistor and having two other electrodes, and a second switching transistor (Q 4 ) having a second control electrode for turning on or off the second switching transistor and having two other electrodes, one of the two other electrodes of the first switching transistor being connected to a first connecting point (N 30 ) between the first resistor and the second resistor, one of the two other electrodes of the second switching transistor being connected to a second connecting point (N 31 ) between the third resistor and the fourth resistor, the other of the two other electrodes of the first switching transistor and the other of the two other electrodes of the second switching transistor being commonly connected to the potential-providing terminal (N 32 ), the first control electrode operatively receiving a first internal clock signal (φ B ) and the second control electrode operatively receiving a second internal clock signal (O C ) having a phase different by 180° with respect to the phase of the first internal clock signal, the first and second internal clock signals being synchronous with the operation of the memory device.

Claim 10

A dynamic semiconductor memory device as set forth in claim 8, wherein the first and second switching transistors are operatively in on and off states respectively during a reset interval of the operation of the memory device, and operatively in off and on states respectively during an active interval of the operation of the memory device.

Claim 11

A dynamic semiconductor memory device as set forth in claim 9, wherein the resistance value of the first resistor is smaller than the resistance value of the second resistor, and the resistance value of the third resistor is greater than the resistance value of the fourth resistor.