Patent EP0112097A2 successfully refreshed from Google Patents.
EP0112097A2
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Polysilicon resistor with low thermal activation energy
Assignee: Thorn EMI North America Inc
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Filing: 1983-12-01
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Granted: —
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Expires: 2003-12-01
Abstract
Abstract A polysilicon resistor with low thermal activation energy for a VLSI memory cell is formed in polysilicon by having P-type (such as boron) impurities in a middle region and n-type (such as phosphorpus or arsenic) impurities on the sides, with the concentrations being in a range so that the thermal activation energy is below about 0.5 eV. Further, the middle region can be doped additionally with arsenic or phosphorous in an amount equal to or less than the boron. This gives good leakage current masking over a range of -55° to +125°C without drawing excessive current, and is less sensitive to impurities.
Inventors
- 👤 Ronald R. Bourassa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 22:27
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; H10P; H10P32/00; H10P32/30; H10P32/302; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
111 words
A polysilicon resistor suitable for use as a load resistor in a VLSI static RAM to permit substantial current masking capability over a temperature test range without drawing excessive current in such range and without drawing excessive power, comprising: a polysilicon region; a selected one of n-type and P-type impurities defining a middle area in said polysilicon region; the other one of said n-type and P-type impurities defining other areas located in said polysilicon region on the sides of said middle area; the concentration of impurities being such that the resistor has a resistance of between about 0.1 and about 50 gigaohms and a thermal activation energy below 0.5 electron volt.
Claim 2
Dependent Claim
111 words
A polysilicon resistor suitable for use as a load resistor in a VLSI static RAM to permit substantial current masking capability over a temperature test range without drawing excessive current in such range and without drawing excessive power, comprising: a polysilicon region; a selected one of n-type and P-type impurities defining a middle area in said polysilicon region; the other one of said n-type and P-type impurities defining other areas located in said polysilicon region on the sides of said middle area; the concentration of impurities being such that the resistor has a resistance of between about 0.1 and about 50 gigaohms and a thermal activation energy below 0.5 electron volt.
Claim 3
Dependent Claim
31 words
A resistor as claimed in Claim 1, wherein said middle area is doped with boron and wherein the other areas are doped with an n-type impurity such as arsenic or phosphorous.
Claim 4
Dependent Claim
24 words
A resistor as claimed in Claim 1 or Claim 2, wherein the concentration of impurities therein is at least 10 17 per cubic centimetre.
Claim 5
Dependent Claim
19 words
A resistor as claimed in any preceding claim, further including both n-type and P-type impurities in said middle area.
Claim 6
Dependent Claim
32 words
A resistor as claimed in Claim 4, wherein the concentration of the impurity which is in said middle area only is equal to or greater than the concentration of the other impurity.
Claim 7
Dependent Claim
60 words
A resistor as claimed in Claim 5, wherein said side areas of polysilicon are doped with an n-type impurity, wherein said middle area is doped with a P-type impurity such as boron, and wherein the concentration of said P-type impurity in said middle area is equal to or greater than the concentration of said n-type impurity in said middle area.
Claim 8
Dependent Claim
48 words
A resistor as claimed in Claim 6-wherein said middle area contains boron impurities doped at a concentration of at least 10 17 per cubic centimetre and wherein said middle region also contains an n-type impurity at a concentration less than the concentration of boron in said middle region.
Claim 9
Dependent Claim
52 words
A resistor as claimed in Claim 2, wherein said middle area consists essentially of polysilicon with boron impurities therein having a concentration of at least 10 17 per cubic centimetre, and wherein said middle area is between two polysilicon areas each having impurities consisting essentially of n-type such as phosphorous or arsenic.
Claim 10
Dependent Claim
26 words
A resistor as claimed in Claim 8, further including a concentration of an n-type impurity in said middle area but less than the concentration of boron.
Claim 11
Dependent Claim
32 words
A resistor as claimed in Claim 9, wherein said middle area contains a concentration of boron and a concentration of arsenic, said arsenic concentration being nearly as great as said boron concentration.
Claim 12
Dependent Claim
113 words
A MOSFET memory cell including two load resistors and two corresponding transistors, each of said resistors being connected to a source of current at one end and coupled to the source of its corresponding transistor at the other end and having a node thereat, said node being coupled to the gate of the other transistor, said cell including a load resistor comprising: a polysilicon area doped with a P-type impurity; two polysilicon areas containing n-type impurities; said P-type area being located between said u-type areas, the concentration of said impurities being so that the thermal activation energy of said resistor is less than 0.5 eV and so that the resistance exceeds 100 megaohms.
Claim 13
Dependent Claim
113 words
A MOSFET memory cell including two load resistors and two corresponding transistors, each of said resistors being connected to a source of current at one end and coupled to the source of its corresponding transistor at the other end and having a node thereat, said node being coupled to the gate of the other transistor, said cell including a load resistor comprising: a polysilicon area doped with a P-type impurity; two polysilicon areas containing n-type impurities; said P-type area being located between said u-type areas, the concentration of said impurities being so that the thermal activation energy of said resistor is less than 0.5 eV and so that the resistance exceeds 100 megaohms.
Claim 14
Independent Claim
64 words
A method for fabricating a resistor element in polysilicon comprising the steps of: providing an insulating layer over single crystal silicon; then depositing a layer of polysilicon over said insulating layer; and placing P-type or n-type impurities in a middle region of said polysilicon; and placing the other one of said P-type or n-type impurities in polysilicon areas next to the above-mentioned polysilicon area.
Claim 15
Independent Claim
64 words
A method for fabricating a resistor element in polysilicon comprising the steps of: providing an insulating layer over single crystal silicon; then depositing a layer of polysilicon over said insulating layer; and placing P-type or n-type impurities in a middle region of said polysilicon; and placing the other one of said P-type or n-type impurities in polysilicon areas next to the above-mentioned polysilicon area.
Claim 16
Dependent Claim
72 words
A method as claimed in Claim 12, wherein said latter two steps comprises: doping the polysilicon layer with an n-type dopant; then doping the polysilicon with a P-type dopant at a concentration equal to or greater than the concentration of said n-type dopant applied in the prior step; then masking the resistor area; then doping the unmasked part of said polysilicon with an n-type dopant at a concentration of the P-type dopant.
Claim 17
Dependent Claim
74 words
A method as claimed in Claim 12, wherein said latter two steps comprise: masking a resistor area; then doping the unmasked polysilicon area with an n-type impurity; then masking the entire polysilicon area except the resistor area; then doping said resistor area with an n-type impurity; then doping said resistor area with a P-type impurity having a concentration equal to or greater than the concentration of said n-type impurity in the immediately preceding step.
Claim 18
Dependent Claim
50 words
A method as claimed in Claim 12, wherein said latter two steps comprise: doping the polysilicon with an n-type dopant; then masking all of the polysilicon except the resistor area; then doping the resistor area with a P-type dopant at a concentration greater than the concentration of the n-type dopant.
References Cited (Backward Citations)
No citation records indexed.
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