EP0111097A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for making semiconductor devices having a thick field dielectric and a self-aligned channel stopper
Assignee: International Business Machines Corp
•
Filing: 1983-10-11
•
Granted: —
•
Expires: 2003-10-11
Abstract
Abstract A method for forming semiconductor devices, for example, FET devices in which the field oxide (14A, B) and ion implanted channel stopper (22A, B) are self-aligned. The method includes the steps of forming a first photoresist (16A, B) etch mask over a thick, i.e. field, oxide on a wafer; etching exposed oxide, forming a complementary-image ion implant mask (20A) over etched active device areas, and ion (24) implanting a channel stopper layer (22A, B) at the interface between the field oxide and the wafer (12) surface.
Inventors
- 👤 Dinesh Arvindlal Badami
- 👤 Albert Stephen Bergendahl
- 👤 Mark Charles Hakey
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 12:33
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/112; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/10; H10W10/13
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
96 words
A method of providing device isolation regions in a semiconductor substrate (12) comprising the steps of: providing a field dielectric layer (14) on said substrate (FIG. 2A), providing a patterned first masking layer (16A, B) over regions of the substrate intended to be field regions (FIG. 2B), etching the exposed areas of the field dielectric layer (FIGS. 2C, 2CC), forming a complementary patterned second masking layer (20, 20A) over etched areas (FIGS. 2D, 2E, 2F), and providing channel stcpper regions (22A, B) under the remaining field dielectric layer using said second layer (20) as a mask.
Claim 2
Independent Claim
96 words
A method of providing device isolation regions in a semiconductor substrate (12) comprising the steps of: providing a field dielectric layer (14) on said substrate (FIG. 2A), providing a patterned first masking layer (16A, B) over regions of the substrate intended to be field regions (FIG. 2B), etching the exposed areas of the field dielectric layer (FIGS. 2C, 2CC), forming a complementary patterned second masking layer (20, 20A) over etched areas (FIGS. 2D, 2E, 2F), and providing channel stcpper regions (22A, B) under the remaining field dielectric layer using said second layer (20) as a mask.
Claim 3
Dependent Claim
14 words
The method of claim 1, whereby said substrate is silicon, in particular p-type silicon.
Claim 4
Dependent Claim
22 words
The method of claim 1, whereby said dielectric layer (14) is silicon dioxide obtained by wet thermal oxidation or chemical vapor deposition.
Claim 5
Dependent Claim
40 words
The method of claim 1, whereby said patterned first masking layer (16A, B) is a resist material that is more sensitive to the exposure or developing technique than the resist material used for the complementary second masking layer (20, 20A).
Claim 6
Dependent Claim
22 words
The method of claim 1, wherein the channel stopper regions (22A, B) are formed by exposing the structure to ion (24) implantation.
Claim 7
Independent Claim
121 words
A method of providing device isolation regions in a semiconductor substrate (12) comprising the steps of: growing a dielectric layer (14) on said substrate, applying, exposing and developing a photoresist pattern (16A, B) to expose areas on said dielectric layer, baking said photoresist pattern, etching said exposed dielectric areas, applying a layer of self-leveling photoresist (20) over said exposed dielectric areas and said baked photoresist pattern, removing the self-leveling photoresist material that is on top of said baked photoresist pattern, dissolving said baked photoresist pattern to leave a plug (20A) of said self-leveling photoresist extending above the surface of said dielectric layer, ion-implanting channel stopper ions (24) through said dielectric layer into said substrate, and removing said plug of self-leveling photoresist.
Claim 8
Independent Claim
121 words
A method of providing device isolation regions in a semiconductor substrate (12) comprising the steps of: growing a dielectric layer (14) on said substrate, applying, exposing and developing a photoresist pattern (16A, B) to expose areas on said dielectric layer, baking said photoresist pattern, etching said exposed dielectric areas, applying a layer of self-leveling photoresist (20) over said exposed dielectric areas and said baked photoresist pattern, removing the self-leveling photoresist material that is on top of said baked photoresist pattern, dissolving said baked photoresist pattern to leave a plug (20A) of said self-leveling photoresist extending above the surface of said dielectric layer, ion-implanting channel stopper ions (24) through said dielectric layer into said substrate, and removing said plug of self-leveling photoresist.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.