Patent EP0110160A2 successfully refreshed from Google Patents.
EP0110160A2
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Floating-point arithmetic operation system
Assignee: Toshiba Corp
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Filing: 1983-10-28
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Granted: —
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Expires: 2003-10-28
Abstract
Abstract A floating-point arithmetic operation system performing an arithmetic operation on two given operands X, Y and providing the result Z of the arithmetic operation, the operands X and Y being each classified according to their attributes; and at least part of the bits of the operand X, at least part of the bits of the operand Y or a predetermined set of bits being adopted as at least part of the result Z of the operation when the results of the classifications are one of predetermined combinations.
Inventors
- 👤 Akira Kanuma
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 15:22
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
169 words
A floating-point arithmetic operation system performing an arithmetic operation on two given operands X, Y and providing the result Z of the arithmetic operation, characterised by: an X classification circuit (3) receiving at least part of the bits representing the operand X to classify the operand X and producing at least one X class signal indicative of the result of the classification; a Y classification circuit (4) receiving at least part of the bits representing the operand Y to classify the operand Y and producing at least one Y class signal indicative of the result of the classification; and adopting means (20) responsive to the X class signal, and Y class signal for adopting, at least part of the bits of the operand X, at least part of the bits of the operand Y or a predetermined set of bits, as at least part of the result Z of the operation when the significances of the X class signal and the Y class signal form one of predetermined combinations.
Claim 2
Dependent Claim
169 words
A floating-point arithmetic operation system performing an arithmetic operation on two given operands X, Y and providing the result Z of the arithmetic operation, characterised by: an X classification circuit (3) receiving at least part of the bits representing the operand X to classify the operand X and producing at least one X class signal indicative of the result of the classification; a Y classification circuit (4) receiving at least part of the bits representing the operand Y to classify the operand Y and producing at least one Y class signal indicative of the result of the classification; and adopting means (20) responsive to the X class signal, and Y class signal for adopting, at least part of the bits of the operand X, at least part of the bits of the operand Y or a predetermined set of bits, as at least part of the result Z of the operation when the significances of the X class signal and the Y class signal form one of predetermined combinations.
Claim 3
Dependent Claim
70 words
A system according to claim 1 characterised in that said adopting means comprises: a control logic circuit (25,27j responsive to the X class signal and the Y class signal for producing a set of control signals; and selecting nears (24,26) receiving, as the inputs, the operand X, the operand Y and at least one predetermined set of bits and selecting one of the inputs in accordance with the control signals.
Claim 4
Dependent Claim
51 words
3 . A system according to claim 2 characterised in that said control logic circuit is also connected to receive a command signal specifying the kind . of arithmetic operation to be performed, and is also dependent on the command signal in determining the significance of said set of control signals.
Claim 5
Dependent Claim
114 words
4 . A system according to claim 1 further characterised by: a normal floating-point arithmetic operation unit (20A) performing an arithmetic operation on the operands X and Y; and a control circuit (25,27) responsive to the X class signal and the Y class signal for producing a set of control signals , wherein said adopting means comprises selecting means (24,26) receiving the result of the arithmetic operation performed by said normal floating-point arithmetic operation unit, at least part of the bits of the operand X, at least part of the bits of the operand Y, and a predetermined set of bits and selectively producing one of the inputs in accordance with the control signals.
Claim 6
Dependent Claim
64 words
A system according to claim 4 characterised in that said normal floating-point arithmetic operation unit comprises a normal floating-point multiplication unit (20A) comprising a mantissa processor (23) performing multiplication on the mantissas of the operands X and Y and normalization where necessary and an exponent processor (22) performing addition of the exponents of the operands X and Y, and adjustment attendant on the normalization.
Claim 7
Dependent Claim
121 words
A system according to claim 1 further characterised by: a normal floating-point arithmetic operation unit (20A) performing an arithmetic operation on the operands X and Y whose classes do not form any of said predetermined combinations; and a control circuit (25,27) responsive to the X class signal and the Y class signal for producing a set of control signals, wherein said adopting means comprises selecting means (24,26) receiving the result of the arithmetic operation performed by said normal floating-point arithmetic operation unit, at least part of the bits of the operand X, at least part of the bits of the operand Y, and a predetermined set of bits and selectively producing one of the inputs in accordance with the control signals.
Claim 8
Dependent Claim
64 words
A system according to claim 6 characterised in that said normal floating-point arithmetic operation unit comprises a normal floating-point multiplication unit (20A) comprising a mantissa processor (23) performing multiplication on the mantissas of the operands X and Y and normalization where necessary and an exponent processor (22) performing addition of the exponents of the operands X and Y, and adjustment attendant on the normalization.
References Cited (Backward Citations)
No citation records indexed.
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