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Patent EP0109308A2 successfully refreshed from Google Patents.
EP0109308A2
Expired / Lapsed
EP
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Block counter system to monitor data transfer
Assignee: Unisys Corp
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Filing: 1983-11-15
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Granted: —
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Expires: 2003-11-15
Abstract
Abstract A system is disclosed which is usable to monitor data-being-transferred in terms of blocks (512 bytes or 256 words) wherein the data-being-transferred is temporarily stored in a RAM buffer memory. Thus, data blocks being transferred from a main host computer to a peripheral terminal unit (as a magnetic tape unit) via a Tape Control Unit (TCU) can be monitored to indicate, at certain intervals, the balance of data residing in the buffer memory during moments between cycles where data has been shifted into and/or shifted out of the buffer memory.
Inventors
- 👤 Jayesh V. Sheth
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 04:42
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/14; G06F13/20; G06F13/28; G06F3/0628; G06F3/0655; G06F3/0656
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
109 words
A system for monitoring the status of data-in-transit between a peripheral unit and a main host system, said system comprising: (a) memory means for temporary data storage, said memory means connected to receive data from and to transmit data to, both said main host system and said peripheral unit; (b) counter means for maintaining a current status signal which indicates the amount of data residing in temporary storage in said memory means; (c) logic circuit means for providing signal data to said counter means, said circuit means indicating the number of data blocks received by said memory means and the number of data blocks transmitted from said memory means.
Claim 2
Independent Claim
109 words
A system for monitoring the status of data-in-transit between a peripheral unit and a main host system, said system comprising: (a) memory means for temporary data storage, said memory means connected to receive data from and to transmit data to, both said main host system and said peripheral unit; (b) counter means for maintaining a current status signal which indicates the amount of data residing in temporary storage in said memory means; (c) logic circuit means for providing signal data to said counter means, said circuit means indicating the number of data blocks received by said memory means and the number of data blocks transmitted from said memory means.
Claim 3
Dependent Claim
71 words
The system of claim 1 wherein said logic circuit means provides said signal data during two conditions of data transfer operations, said conditions including: (2a) read operations wherein data is transferred from a peripheral unit to said memory means for subsequent transfer to said main host computer system; (2b) write operations wherein data is transferred from said main host system to said memory means for subsequent transfer to said peripheral unit.
Claim 4
Dependent Claim
125 words
The system of claim 1 wherein said logic circuit means includes: (3a) address register means for receiving address data to be used in accessing locations in said memory means and for providing numerical data signals to a block counter logic unit wherein said numerical data signals indicate the amount of data transferred into, and the amount of data transferred out of, said memory means; (3b) a block counter logic unit connected to receive said numerical data signals from said address register means and to provide firsthand second logic output signals to a gating means; (3c) gating means for permitting output signals to said counter means, said output signals operating to shift up or shift down the count in said counter means at selected clock times.
Claim 5
Dependent Claim
82 words
The system of claim 3 wherein said address register means includes: (4a) peripheral address register means connected to receive address data when data is transferred either from the said memory means to said peripheral unit or when data is transferred from said peripheral unit to said memory means; (4b) system address register means connected to receive address data when data is transferred either from said memory means to said main host system, or from said main host system to said memory means.
Claim 6
Dependent Claim
48 words
The system of claim 3 wherein said logic circuit means includes: (5a) means for signalling said block counter logic unit to indicate the condition of a "Read" operation from the said peripheral unit or a "Write" operation from the said main host computer to the said peripheral unit.
Claim 7
Dependent Claim
79 words
The system of claim 3 wherein said gating means includes: (6a) input connection means from the output of said block counter logic unit to carry logic information indicating an upcount or down-count or no-change for each "Read" operation or for each "Write" operation; (6b) microcode input signals for diagnostic and control operations for said counter means; (6c) first and second output signals, connected to said counter means, for causing said counter means to shift up or to shift down.
Claim 8
Independent Claim
140 words
A system for monitoring the status of data-in-transit between a peripheral unit and a main host system, wherein a peripheral-controller is initiated by instructions from said main host system to manage data transfer operations, and said peripheral-controller includes a common-control circuit unit for sequencing microcode instructions and a peripheral dependent circuit unit for interfacing said peripheral unit, the status-monitoring system comprising: (7a) buffer memory means for temporarily storing data-in-transit between said main host system and said peripheral unit; (7b) counter means for carrying a current status signal which indicates the number of blocks of data residing in said buffer memory means during any given clock cycle; (7c) logic circuit means for raising or lowering the said status signal in said counter means according to address data signals which insert or remove data into or out of said buffer memory means;
Claim 9
Independent Claim
140 words
A system for monitoring the status of data-in-transit between a peripheral unit and a main host system, wherein a peripheral-controller is initiated by instructions from said main host system to manage data transfer operations, and said peripheral-controller includes a common-control circuit unit for sequencing microcode instructions and a peripheral dependent circuit unit for interfacing said peripheral unit, the status-monitoring system comprising: (7a) buffer memory means for temporarily storing data-in-transit between said main host system and said peripheral unit; (7b) counter means for carrying a current status signal which indicates the number of blocks of data residing in said buffer memory means during any given clock cycle; (7c) logic circuit means for raising or lowering the said status signal in said counter means according to address data signals which insert or remove data into or out of said buffer memory means;
Claim 10
Dependent Claim
46 words
The status monitoring system of claim 7 which includes: (8a) address data signals, from said common-control circuit unit, and connected for transmittal to said logic circuit means, for logical operations 5 which determine the amount of data removed from or inserted into said buffer memory means.
Claim 11
Dependent Claim
41 words
The system of claim 8 which includes: (9a) output flip-flop means receiving signals from said counter means, said flip-flop means providing output information signals to said common-control circuit unit upon the occurrence of specified numerical conditions occurring in said counter means.
Claim 12
Dependent Claim
54 words
The system of claim 9 wherein said output flip-flop means provides an output information signal when: (l0a) the count in said counter means is equal to "X" indicating that the said buffer memory means is full, where "X" represents the number of data blocks filling the maximum data capacity of said buffer memory means.
Claim 13
Dependent Claim
36 words
The system of claim 9 wherein said output flip-flop means provides an output information signal when: (lla) the count in said counter means is equal to "0" denoting that the said buffer memory means is empty.
References Cited (Backward Citations)
No citation records indexed.
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