Self-testing method for logic circuitry

Claim 1

Self-testing method for combinatorial and sequential logic circuitry with memory circuits (16) on individual logic units (10), the memory circuits, when coupled together, forming shift register scan paths (18) for testing associated logic circuits (20) and, when decoupled, disabling the scan paths while the logic circuits are performing their designed logic functions, the method using a multistage generator means to generate testing sequences, and multistage data compressing means to compress the responses of the logic circuits (20), and being characterized in that it comprises the following steps - forming the shift register scan paths (18) on the logic units into a single linear feedback shift register that is capable of operating as a multistage random signal generator and as a multistage data compression means, - shifting data through the linear feedback shift register so that it simultaneously supplies test signals to the associated logic circuits and captures the responses of the logic circuit to the shifted test data, - reading the contents of the linear feedback shift register out of the scan path as the test result.