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EP0106670A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

CPU with multiple execution units

Assignee: Bull HN Information Systems Italia SpA
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Filing: 1983-10-13
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Granted: —
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Expires: 2003-10-13
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Abstract

Abstract A collector for the results of a pipelined central processing unit of a digital data processing system. The processor has a plurality of execution units 24, 26, 28, 30, with each execution unit executing a different set of instructions of the instruction repertoire of the processor. The execution units execute instructions issued to them in order of issuance by the pipeline 12 and in parallel. As instructions are issued to the execution units, the operation code identifying each instruction is also issued in program order to an instruction execution queue 18 of the collector. The results of the execution of each instruction by an execution unit are stored in a result stack 38, 40, 42, 44 associated with each execution unit. Collector control 46 causes the results of the execution of instructions to program visible registers to be stored in a master safe store register 48 in program order which is determined by the order of instructions stored in the instruction execution stack on a first-in, first-out basis. The collector also issues write commands to write results of the execution of instructions into memory in program order via a store stack 50.

Inventors

  • 👤 Russell W. Guenthner
  • 👤 Leonard G. Trubisky
  • 👤 Joseph C. Circello
  • 👤 Gregory C. Edgington

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 20:21
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3861; G06F9/3863

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 129 words
A central processing unit (CPU) comprising a plurality of execution units (24-30) each of which executes a different subset of the repertoire of instructions of the CPU, the CPU including means (12,22) for issuing instructions to the appropriate execution units in program order, characterized by a plurality of result stacks (38-44), each associated with a respective execution unit; an instruction execution queue stack (18) in which the instructions issued to all the execution units are stored in program order; store means (48,50) for storing the results of instructions executed by the execution units; and control means (47) responsive to the order in which the instructions are stored in the instruction execution queue stack to pass the results in the results stacks to the store means in the appropriate order.
Claim 2
Dependent Claim 129 words
A central processing unit (CPU) comprising a plurality of execution units (24-30) each of which executes a different subset of the repertoire of instructions of the CPU, the CPU including means (12,22) for issuing instructions to the appropriate execution units in program order, characterized by a plurality of result stacks (38-44), each associated with a respective execution unit; an instruction execution queue stack (18) in which the instructions issued to all the execution units are stored in program order; store means (48,50) for storing the results of instructions executed by the execution units; and control means (47) responsive to the order in which the instructions are stored in the instruction execution queue stack to pass the results in the results stacks to the store means in the appropriate order.
Claim 3
Dependent Claim 21 words
A CPU according to claim 1, characterized in that the instruction execution queue stack stores the op codes of the instructions.
Claim 4
Dependent Claim 25 words
A CPU according to either previous claim, characterized in that all or all but one of the execution units has a respective input stack (32-36).
Claim 5
Dependent Claim 41 words
A CPU according to any previous claim characterized in that store means comprise a master safe store (48) in which program visible registers are stored and a store stack (50) through which data to be stored in main memory is passed.
Claim 6
Dependent Claim 53 words
A CPU according to any previous claim characterized in that the control means is responsive to the detection of a fault in the results from any of the execution units or an interrupt to prevent the passage into the store means of any results following the fault in program order or the interrupt.

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