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EP0106617A2
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EP
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Method for fabricating an EEPROM
Assignee: Fujitsu Ltd
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Filing: 1983-10-04
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Granted: —
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Expires: 2003-10-04
Abstract
Abstract A floating-gate tunnel-injection type EEPROM having an excellent quality tunneling insulating layer (19) is fabricated by forming an impurity-doped region (28) under the tunneling insulating layer by diffusion from a neighboring region (26, 27). The impurity-doped region (28) under the tunneling insulating layer (19) does not have an edge under the tunneling insulating layer. The substrate (13) under the tunneling insulating layer (19) is not damaged by any previous ion implantation process. Thus excellent operation of the EEPROM is enabled.
Inventors
- 👤 Yoshihiro Oshikawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 16:18
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
85 words
A method for fabricating a floating-gate tunnel-injectiontype electrically erasable programmable read only memory, including the steps of: forming a tunneling insulating layer on a semiconductor substrate; forming a floating gate extending onto the tunneling insulating layer; and then introducing a doping impurity into a first region of the substrate neighboring the floating gate on the tunneling insulating layer as well as into an entire second region of the substrate just under the tunneling insulating layer under the floating gate by diffusion from the first region.
Claim 2
Independent Claim
85 words
A method for fabricating a floating-gate tunnel-injectiontype electrically erasable programmable read only memory, including the steps of: forming a tunneling insulating layer on a semiconductor substrate; forming a floating gate extending onto the tunneling insulating layer; and then introducing a doping impurity into a first region of the substrate neighboring the floating gate on the tunneling insulating layer as well as into an entire second region of the substrate just under the tunneling insulating layer under the floating gate by diffusion from the first region.
Claim 3
Dependent Claim
59 words
A method according to claim 1, wherein the step of introducing a doping impurity into the first region as well as into the entire second region comprises a first process of ion implanting the doping impurity into the first region and a second process of heat diffusing the doping impurity to the entire second region from the first region.
Claim 4
Dependent Claim
47 words
A method according to claim 1, wherein the step of introducing a doping impurity into the first region as well as into the entire second region is completed by a single process of heat diffusion of the doping impurity through the top surface of the first region.
Claim 5
Dependent Claim
56 words
A method according to claim 1, wherein the doping impurity is introduced into the first region of the substrate of both sides of the floating gate as well as into the entire second region of the substrate just under the tunneling insulating layer under the floating gate by diffusion from both sides of the second region.
Claim 6
Dependent Claim
26 words
A method according to claim 1, wherein the floating gate on the tunneling insulating layer has a width of from about 1 µm to 2 µm.
Claim 7
Dependent Claim
15 words
A method according to claim 1, wherein the tunneling insulating layer is of silicon dioxide.
References Cited (Backward Citations)
No citation records indexed.
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