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EP0105724A2
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Data write arrangement for color graphic display unit
Assignee: Fanuc Corp
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Filing: 1983-09-29
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Granted: —
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Expires: 2003-09-29
Abstract
Abstract A plurality of color graphic memories (41,51,61) are assigned the same address space, and are connected to a common data bus (X1). It is determined by a separately output memory select data which one of the color graphic memories (41,51,61) is to be written into. In the case of writing the same data into two or more of the color graphic memories (41,51,61) at the same address, the color graphic memories to be written into are selected by the memory select data first and then the same data is written into the selected colour graphic memories in the same write cycle.
Inventors
- 👤 Yoshiaki Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 14:22
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/02; G09G5/022
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
74 words
A data write arrangement for a color graphic display unit, comprising a plurality of color graphic memories assigned the same address space, addressing means for addressing the space in the color graphic memories, data write means for outputting data to be written into the addressed space of at least one of the color graphic memories, and memory select means for selecting which one or more of the color graphic memories will receive said data.
Claim 2
Dependent Claim
74 words
A data write arrangement for a color graphic display unit, comprising a plurality of color graphic memories assigned the same address space, addressing means for addressing the space in the color graphic memories, data write means for outputting data to be written into the addressed space of at least one of the color graphic memories, and memory select means for selecting which one or more of the color graphic memories will receive said data.
Claim 3
Dependent Claim
50 words
A data write arrangement according to claim 1, which is adapted and arranged such that in operation of the arrangement the memory select means outputs memory select data and then the addressing means and the data write means output an address signal and data respectively for the color graphic memories.
Claim 4
Dependent Claim
52 words
A data write arrangement according to claim 1 or 2, wherein the memory select means comprises a chip select circuit for generating a chip select signal by logical processing of outputs from a latch circuit for latching memory select data, and from an address decoder for decoding a chip select address signal.
Claim 5
Dependent Claim
43 words
A data write arrangement according to claims 1, 2 and 3 combined, wherein when the arrangement is in operation the memory select data, the memory address signal, the memory data and the chip select address signal are all generated from the same source.
Claim 6
Dependent Claim
14 words
A data write arrangement according to claim 4, wherein said source is a microcomputer.
References Cited (Backward Citations)
No citation records indexed.
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