Patent EP0105710A2 successfully refreshed from Google Patents.
EP0105710A2
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Method for recovering from error in a microprogram-controlled unit
Assignee: Fujitsu Ltd
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Filing: 1983-09-28
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Granted: —
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Expires: 2003-09-28
Abstract
Abstract An erroneous microinstruction and related preceding microinstructions are subjected to a so-called retry operation so as to restore the microprogram-controlled unit from the error. The retry operation is carried out under an interlock mode, in which both detection of the erroneous microinstruction and correction for each microinstruction are achieved. At the same time, an address for specifying the thus detected erroneous microinstruction is recorded. When an address the same as the recorded address is next generated, the recovery from the error is performed only for the erroneous microinstruction under the interlock mode.
Inventors
- 👤 Kiyosumi Gurin-Kopo B511 Sato
- 👤 Kazuyuki Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 18:15
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/141; G06F9/00; G06F9/06; G06F9/22
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
196 words
A method for recovering from an error in a microprogram-controlled unit, the microprogram-controlled unit being comprised of at least a control storage for storing microinstructions, a control storage address register storing an address for specifying the microinstruction, a microinstruction register, and other serially-connected registers, as tags, in multistage with the microinstruction register, and an error detection and correction circuit operative to check a validity of each microinstruction stored in the initial register and correct an erroneous microinstruction to be restored in the microinstruction register, in which the error check by the error detection and correction circuit for each microinstruction is carried out in parallel with execution of each microinstruction, which method comprises the operations of: (a) detecting whether or not each microinstruction includes an error; (b) performing a retry operation for the related microinstructions including the detected erroneous microinstruction under an interlock mode, in which interlock mode the erroneous microinstruction and the related preceding microinstructions are successively subjected to error detection and correction, followed by reexecution; (c) recordina an address specifying the erroneous microinstruction; and (d) performing an interlock mode operation for only the erroneous microinstruction when the address for the erroneous microinstruction is again accessed.
Claim 2
Independent Claim
196 words
A method for recovering from an error in a microprogram-controlled unit, the microprogram-controlled unit being comprised of at least a control storage for storing microinstructions, a control storage address register storing an address for specifying the microinstruction, a microinstruction register, and other serially-connected registers, as tags, in multistage with the microinstruction register, and an error detection and correction circuit operative to check a validity of each microinstruction stored in the initial register and correct an erroneous microinstruction to be restored in the microinstruction register, in which the error check by the error detection and correction circuit for each microinstruction is carried out in parallel with execution of each microinstruction, which method comprises the operations of: (a) detecting whether or not each microinstruction includes an error; (b) performing a retry operation for the related microinstructions including the detected erroneous microinstruction under an interlock mode, in which interlock mode the erroneous microinstruction and the related preceding microinstructions are successively subjected to error detection and correction, followed by reexecution; (c) recordina an address specifying the erroneous microinstruction; and (d) performing an interlock mode operation for only the erroneous microinstruction when the address for the erroneous microinstruction is again accessed.
Claim 3
Dependent Claim
51 words
A method as set forth in claim 1, wherein the reaccessing of the address for the erroneous microinstruction is detected by comparing each address in said control storage address register with said recorded address specifying the erroneous microinstruction, which recorded address has been stored in an error address storing register. '
Claim 4
Dependent Claim
21 words
A method as set forth in claim 2, wherein said address to be recorded is for fixedly occurring erroneous microinstructions only.
Claim 5
Dependent Claim
37 words
A method as set forth in claim 3, wherein said error address storing register records the same address stored in said control storage address register just at time the error is detected in said operation of (b).
Claim 6
Dependent Claim
31 words
A method as set forth in claim 1, wherein said interlock mode is created by doubling a certain one of the steps each defined by a machine cycle of said unit.
References Cited (Backward Citations)
No citation records indexed.
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