Patent EP0104859A2 successfully refreshed from Google Patents.
EP0104859A2
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EP
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Multiprocessor memory map
Assignee: Xerox Corp
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Filing: 1983-09-19
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Granted: —
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Expires: 2003-09-19
Abstract
Abstract The present invention provides RAM locations in a main processor to store the inputs from other input/output processors. Thus, inputs to an input/output processor are also conveyed over a communication channel to the main processor and stored in the main processor's RAM. All control functions or processors needing a particular input value or responding to certain input values, would look to the input values stored in the master processor memory rather than in the local input/output processor. Inputs to any particular input/output processor or control code relying on the inputs can then be shifted to other processors. This would not effect the control since the control responds to the inputs centrally located in the master processor RAM.
Inventors
- 👤 Ernest Lee Legg
- 👤 Anthony Michael Federico
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 21:42
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/177; G06F13/00; G06F13/14; G06F13/20; G06F13/22
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
77 words
An apparatus which comprises a plurality of operating components, a plurality of control devices for controlling operation of said operating components, one of said control devices being a master processor with a related memory and one of said control devices being an input/output processor , providing input data, a communication channel, said master and said input/output processor being connected to the communication channel, and means to store the input data from the input/output processor in said memory.
Claim 2
Independent Claim
77 words
An apparatus which comprises a plurality of operating components, a plurality of control devices for controlling operation of said operating components, one of said control devices being a master processor with a related memory and one of said control devices being an input/output processor , providing input data, a communication channel, said master and said input/output processor being connected to the communication channel, and means to store the input data from the input/output processor in said memory.
Claim 3
Dependent Claim
35 words
An apparatus according to claim 1 wherein said input data is from a specified input source and the storing means maps the data onto a portion of said memory corresponding to the specified source. -
Claim 4
Dependent Claim
42 words
An apparatus according to claim 1 or 2 including a plurality of input/output processors, the storing means mapping input data from each of the input/output processors and related to respective sources onto respective portions of said memory corresponding to said specified sources.
Claim 5
Dependent Claim
47 words
An apparatus according to claim 3 including a first input/output processor having an input A, a second input/output processor. responding to input A, and means for enabling the second input/output processor to respond to input A, input A being stored in said memory by said storing means.
Claim 6
Dependent Claim
18 words
An apparatus according to claim 3 or 4 wherein said processors are interconnected via a shared communication line.
Claim 7
Independent Claim
159 words
An apparatus which comprises a plurality of operating components cooperating with one another to produce a result, and a system controller for controlling the operating components, said controller comprising: a plurality of control devices, one of said control devices being a master processor with a related memory and one of said control devices being a remote processor, an input data source connected to one of said operating components and providing control information to said remote processor, a communication channel, said master processor and said remote processor being connected to the communication channel, said remote processor conveying said control information to the master processor via the channel, and means to store the control information from the remote processor in a portion of the memory of the master processor designated for said input data source whereby said control infonnation is accessible by any other control device and identified to said other control devices as being provided by said input data source.
Claim 8
Independent Claim
159 words
An apparatus which comprises a plurality of operating components cooperating with one another to produce a result, and a system controller for controlling the operating components, said controller comprising: a plurality of control devices, one of said control devices being a master processor with a related memory and one of said control devices being a remote processor, an input data source connected to one of said operating components and providing control information to said remote processor, a communication channel, said master processor and said remote processor being connected to the communication channel, said remote processor conveying said control information to the master processor via the channel, and means to store the control information from the remote processor in a portion of the memory of the master processor designated for said input data source whereby said control infonnation is accessible by any other control device and identified to said other control devices as being provided by said input data source.
Claim 9
Independent Claim
161 words
An apparatus comprising a plurality of operating components and a system controller for controlling the operating components, said controller comprising: a plurality of control devices for activating the operating components, each of the control devices including an arithmetic and logic unit for manipulating data; one of the control devices being a master processor with memory the other control devices being input/output processors; an input data source connected to one of the operating components for producing control information to one of the input/output processors, said memory having a portion dedicated to said input data source, a shared communication line, each of the control devices being interconnected to the shared communication line for data communication between the control devices; said input/output processor conveying said control information to the master processor via the communication line, and means to store the control information in the memory portion dedicated to the input data source whereby said control information is accessible by all the other input/output processors.
Claim 10
Independent Claim
161 words
An apparatus comprising a plurality of operating components and a system controller for controlling the operating components, said controller comprising: a plurality of control devices for activating the operating components, each of the control devices including an arithmetic and logic unit for manipulating data; one of the control devices being a master processor with memory the other control devices being input/output processors; an input data source connected to one of the operating components for producing control information to one of the input/output processors, said memory having a portion dedicated to said input data source, a shared communication line, each of the control devices being interconnected to the shared communication line for data communication between the control devices; said input/output processor conveying said control information to the master processor via the communication line, and means to store the control information in the memory portion dedicated to the input data source whereby said control information is accessible by all the other input/output processors.
Claim 11
Dependent Claim
14 words
An apparatus according to claim 7 wherein said input data source is a switch.
Claim 12
Dependent Claim
14 words
An apparatus according to claim 7, wherein said input data source is a sensor.
Claim 13
Independent Claim
15 words
An apparatus according to any of claims 1 to 9 when an electrophotographic copying apparatus.
References Cited (Backward Citations)
No citation records indexed.
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