Patent EP0104545A2 successfully refreshed from Google Patents.
EP0104545A2
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EP
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Input and output port control unit
Assignee: Toshiba Corp
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Filing: 1983-09-14
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Granted: —
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Expires: 2003-09-14
Abstract
Abstract An input and output port control unit which is adapted to a microcomputer system including an interrupt request line (19), address/control bus (15) and data bus (17), a plurality of extension boards (13i), each board (13i) including an I/0 logic circuit (23) for producing an interrupt request signal. The interrupt request signal is transferred to the microcomputer system through an interrupt request flip-flop (27), NAND gate (35) and a common interrupt request line (19). The microcomputer, in response to the interrupt request signal outputs a common port address to those extension boards (13i) through an address/control bus (15). The common port address is decoded by a decoder (25). The output signal from the decoder (25) and the interrupt request signal form an interrupt request identifying signal with a flip-flop (29) and NAND gates (31, 33). The interrupt request identifying signal is transferred through a predetermined bit line of a data bus (17) to the microcomputer system.
Inventors
- 👤 Takatoshi Ishii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 19:49
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F12/00; G06F12/02; G06F12/06; G06F12/0615; G06F12/063
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
146 words
An input and output port control unit adapted to a computer system including an interrupt request line (19), address/control bus (15) and data.bus (17), including a plurality of extension boards (13i), each board (13i) comprising: interface means (23) which interfaces with said computer system; first transfer means (27, 35, 19) for transferring through the interrupt request line an interrupt request signal from said interface means to said computer system; means for producing through the address control bus a port address which is common for all the extension boards from said computer system; decoding means (25) for decoding the common port address; and second transfer means (31, 33, 17) for transferring an interrupt-request-identifying signal driven from the output signal of said decoder and the interrupt request signal to said computer system through a specified bit of the data bus assigned to said input and output control unit.
Claim 2
Dependent Claim
146 words
An input and output port control unit adapted to a computer system including an interrupt request line (19), address/control bus (15) and data.bus (17), including a plurality of extension boards (13i), each board (13i) comprising: interface means (23) which interfaces with said computer system; first transfer means (27, 35, 19) for transferring through the interrupt request line an interrupt request signal from said interface means to said computer system; means for producing through the address control bus a port address which is common for all the extension boards from said computer system; decoding means (25) for decoding the common port address; and second transfer means (31, 33, 17) for transferring an interrupt-request-identifying signal driven from the output signal of said decoder and the interrupt request signal to said computer system through a specified bit of the data bus assigned to said input and output control unit.
Claim 3
Dependent Claim
49 words
An input and output port control unit according to claim 1, characterized in that said computer system includes a discriminating means (RDID) for discriminating said extension board which has produced the interrupt request signal by discriminating the active bits of the interrupt-request-identifying signal transferred through the data bus (17).
Claim 4
Dependent Claim
51 words
An input and output port control unit according to claim 1, characterized in that when the interrupt request signals are produced simultaneously from a plurality of extension boards, said computer system identifies the plurality of active bits of the interrupt request identifying signal in a priority order set by a program.
Claim 5
Dependent Claim
160 words
An input and output control unit adapted to a computer system including an interrupt request line, address/control bus and data bus, including a plurality of extension boards, each board comprising: means (10) for producing first and second port addresses which are common to the extension boards through the address/control bus; decoding means (16) for decoding the first and second port addresses; latch means (165) which is set by a decoded signal of the first port address from said decoding means and is reset by a signal through a specified bit of the data bus from said computer system; output gate means (166, 167) which receives an output signal from said latch means and an output signal of the second port address from said decoder; and transferring means (151) for transferring an output signal from said output gate means to said computer system through the specified bit of the data bus assigned to the extension board as a mounting identifying signal.
Claim 6
Dependent Claim
160 words
An input and output control unit adapted to a computer system including an interrupt request line, address/control bus and data bus, including a plurality of extension boards, each board comprising: means (10) for producing first and second port addresses which are common to the extension boards through the address/control bus; decoding means (16) for decoding the first and second port addresses; latch means (165) which is set by a decoded signal of the first port address from said decoding means and is reset by a signal through a specified bit of the data bus from said computer system; output gate means (166, 167) which receives an output signal from said latch means and an output signal of the second port address from said decoder; and transferring means (151) for transferring an output signal from said output gate means to said computer system through the specified bit of the data bus assigned to the extension board as a mounting identifying signal.
Claim 7
Dependent Claim
62 words
An input and output control unit in a computer system in which input and output units connected to said system are defined as pages (input and output pages), an input and output port is commonly assigned to the pages to extend the input and output port wherein said respective page is provided with input and output page selecting means (34, 35, 36).
Claim 8
Dependent Claim
62 words
An input and output control unit in a computer system in which input and output units connected to said system are defined as pages (input and output pages), an input and output port is commonly assigned to the pages to extend the input and output port wherein said respective page is provided with input and output page selecting means (34, 35, 36).
Claim 9
Dependent Claim
103 words
An input and output control unit according to claim 5, wherein said input and output page selecting means comprises: a first decoder (34) for decoding an address specified by a processor unit; an input and output page selecting circuit (35) in which data for the page selection is set for each the input and output page and the selected data is loaded in accordance with the output of the first decoder; and a second decoder (36), enabled by the output from said input and output page selecting circuit for decoding the common input and output port within the specified input and output page.
References Cited (Backward Citations)
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