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Patent EP0104079A2 successfully refreshed from Google Patents.
EP0104079A2
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EP
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Integrated circuit contact structure
Assignee: International Business Machines Corp
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Filing: 1983-09-20
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Granted: —
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Expires: 2003-09-20
Abstract
Abstract A multi-layer contact structure is described for providing ohmic contact to a shallow semiconductor region (12) forming a PN junction with a silicon semiconductor body (10). The multi-layer structure includes a layer of polycrystalline silicon (22) doped with an impurity of the same conductivity type as that of the semiconductor region (12). A first layer (26) of a refractory metal is deposited over the polycrystalline silicon layer (22) to provide an electrically stable interface therewith. A second layer (28) of another refractory metal is deposited over the first refractory metal layer and serves to protect the shallow PN junction against current leakage failure. A third layer (34) of interconnect metal such as aluminium is deposited over the refractory metal layer.
Inventors
- 👤 Mohamed Osama Aboelfotoh
- 👤 Yuk Lun Tsang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 20:38
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10W; H10W20/00; H10W20/40
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
129 words
An integrated circuit ohmic contact structure for a shallow semiconductor region (12) provided in the surface of, and forming a PN junction with, a surrounding silicon semiconductor body (10), characterised by an insulating layer (16) formed on the surface of the silicon semiconductor body, the insulating layer having a contact window (18) exposing the shallow semiconductor region (12), a polycrystalline silicon layer (22) formed in the contact window (18) and overlapping the edges thereof, the polycrystalline silicon layer (22) being doped with an impurity of the same conductivity type as that of the semiconductor region (12), a plurality of layers (26, 28) of refractory metal formed on the polycrystalline silicon layer (22), and a layer (34) of interconnect metal formed on the upper surface of the refractory metal layers.
Claim 2
Dependent Claim
129 words
An integrated circuit ohmic contact structure for a shallow semiconductor region (12) provided in the surface of, and forming a PN junction with, a surrounding silicon semiconductor body (10), characterised by an insulating layer (16) formed on the surface of the silicon semiconductor body, the insulating layer having a contact window (18) exposing the shallow semiconductor region (12), a polycrystalline silicon layer (22) formed in the contact window (18) and overlapping the edges thereof, the polycrystalline silicon layer (22) being doped with an impurity of the same conductivity type as that of the semiconductor region (12), a plurality of layers (26, 28) of refractory metal formed on the polycrystalline silicon layer (22), and a layer (34) of interconnect metal formed on the upper surface of the refractory metal layers.
Claim 3
Dependent Claim
15 words
A structure as claimed in Claim 1, wherein the insulating layer (16) comprises silicon dioxide.
Claim 4
Dependent Claim
24 words
A structure as claimed in Claim 1 or 2, wherein the thickness of the polycrystalline silicon layer (22) is from 3,000 to 5,000 Angstroms.
Claim 5
Dependent Claim
31 words
A structure as claimed in Claim 3, wherein the doping level of the impurity in the polycrystalline silicon layer (22) is from 10 19 to 10 21 atoms per cubic centimetre.
Claim 6
Dependent Claim
33 words
A structure as claimed in any preceding Claim, wherein the plurality of layers of refractory metal comprises a first layer (26) of a titanium/tungsten alloy comprising 10 to 30 percent by weight tungsten.
Claim 7
Dependent Claim
36 words
A structure as claimed in Claim 5, wherein the plurality of layers of refractory metal further includes a second layer (28) of tantalum, tungsten or a titanium/tungsten alloy comprsing at least 70 percent by wight tungsten.
Claim 8
Dependent Claim
26 words
A structure as claimed in Claim 6, wherein the thickness of each of the first and second refractory metal layers is from 500 to 2,000 Angstroms.
Claim 9
Independent Claim
169 words
A method of fabricating an integrated circuit field effect transistor wherein a layer of polycrystalline silicon is formed over a silicon body (10) covered by a first layer of silicon dioxide (42), the polycrystalline silicon layer being selectively etched to form a gate electrode (44), characterised by: chemically vapour depositing a second layer (46) of silicon dioxide over the gate electrode (44), reactive ion etching the first and second silicon dioxide layers (42, 46) to remove the silicon dioxide layers where source and drain regions are desired while leaving a portion of silicon dioxide (46) on the vertical sidewalls of the gate electrode (44), providing source and drain regions (50) adjacent to the gate electrode (44), forming a third layer (52, 54) of silicon dioxide over the source and drain regions (50) and the gate electrode (44), the third layer having contact windows (56) exposing the source and drain regions (50), and providing a respective contact structure to the gate electrode (44) and the source and drain regions (50).
Claim 10
Independent Claim
169 words
A method of fabricating an integrated circuit field effect transistor wherein a layer of polycrystalline silicon is formed over a silicon body (10) covered by a first layer of silicon dioxide (42), the polycrystalline silicon layer being selectively etched to form a gate electrode (44), characterised by: chemically vapour depositing a second layer (46) of silicon dioxide over the gate electrode (44), reactive ion etching the first and second silicon dioxide layers (42, 46) to remove the silicon dioxide layers where source and drain regions are desired while leaving a portion of silicon dioxide (46) on the vertical sidewalls of the gate electrode (44), providing source and drain regions (50) adjacent to the gate electrode (44), forming a third layer (52, 54) of silicon dioxide over the source and drain regions (50) and the gate electrode (44), the third layer having contact windows (56) exposing the source and drain regions (50), and providing a respective contact structure to the gate electrode (44) and the source and drain regions (50).
Claim 11
Dependent Claim
27 words
A method as claimed in Claim 8, wherein the thickness of the chemically vapour deposited second layer (46) of silicon dioxide is from 1,000 to 2,000 Angstroms.
Claim 12
Dependent Claim
68 words
A method as claimed in Claim 8 or 9, wherein the contact structure comprises a polycrystalline silicon layer on the source and drain regions, the polycrystalline layer being doped with an impurity of the same conductivity type as that of the source and drain regions, a plurality of layers of refractory metal on the polycrystalline silicon layer, and a layer of interconnect metal on the refractory metal layers.
References Cited (Backward Citations)
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