Process for integrated circuit metallization with low via resistance

Claim 1

A method of fabricating thin film interconnected metallization (3, 9) on a dielectric coated integrated circuit substrate (1) having ohmic contact via openings through said dielectric coating (2) to elements of a circuit, comprising: heating said substrate (1) in a vacuum environment to a temperature between about 180°C and about 210°C to condition said substrate for deposition of a first level metallization (3); discontinuing- said heating and coincidently initiating evaporation of said first level metallization (3) to deposit, during cooling of said substrate (1), a first aluminum-copper film (3) over said dielectric coating (2) and in said ohmic contact via openings; forming in said first level metallization (3) a predetermined interconnection pattern to said circuit elements; depositing a dielectric layer (4) over said first level metallization (3) and said dielectric coating (2); forming a second pattern of via openings (5) in said dielectric layer (4) to expose selected portions of said first level metallization (3); dry etching to sputter clean said exposed first level metallization (3) and said dielectric layer (4) in an inert atmosphere and at ambient temperatures; initiating evaporation of a second level aluminum- copper film (9) at ambient temperatures over said dielectric layer (4) and in said second vias (5) and coincidentally initiating heating of said substrate (1) to a temperature of between about 150°C and about 210°C over the deposition time of said second level metallization.

Claim 2

A method of fabricating thin film interconnected metallization (3, 9) on a dielectric coated integrated circuit substrate (1) having ohmic contact via openings through said dielectric coating (2) to elements of a circuit, comprising: heating said substrate (1) in a vacuum environment to a temperature between about 180°C and about 210°C to condition said substrate for deposition of a first level metallization (3); discontinuing- said heating and coincidently initiating evaporation of said first level metallization (3) to deposit, during cooling of said substrate (1), a first aluminum-copper film (3) over said dielectric coating (2) and in said ohmic contact via openings; forming in said first level metallization (3) a predetermined interconnection pattern to said circuit elements; depositing a dielectric layer (4) over said first level metallization (3) and said dielectric coating (2); forming a second pattern of via openings (5) in said dielectric layer (4) to expose selected portions of said first level metallization (3); dry etching to sputter clean said exposed first level metallization (3) and said dielectric layer (4) in an inert atmosphere and at ambient temperatures; initiating evaporation of a second level aluminum- copper film (9) at ambient temperatures over said dielectric layer (4) and in said second vias (5) and coincidentally initiating heating of said substrate (1) to a temperature of between about 150°C and about 210°C over the deposition time of said second level metallization.

Claim 7

The method of any of the preceding claims, further including heating the substrate (1) at about 400°C for about 75 minutes to interdiffuse said first and second metallization levels (3, 9) in said second via holes (5).