Patent EP0102608A2 successfully refreshed from Google Patents.
EP0102608A2
Expired / Lapsed
EP
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Expansion circuit for digital signals
Assignee: Hitachi Ltd
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Filing: 1983-08-29
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Granted: —
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Expires: 2003-08-29
Abstract
Abstract A PCM signal processor which converts an analog signal into a digital signal to transmit or record the digital signal. When the PCM signal processor receives a PCM signal whose data has been compressed in such a manner that one or more lower bits are cut off from a plurality of bits for forming the PCM signal and indicating the signal level of the analog signal, in accordance with the signal level of the analog signal, one or more bits corresponding to the number of bits having been cut off are added in the processor to the compressed PCM signal at the position following the least significant bit of the compressed PCM signal (9). Correction data indicating about one half the largest one of numerical values that can be expressed by the added bit or bits, is given to the added bit or bits (30, 31; 26).
Inventors
- 👤 Hiroo Okamoto
- 👤 Tsutomu Noda
- 👤 Takao Arai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 13:31
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30; H03M7/50; H03G; H03G7/00; H03G7/007; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/046; H04B14/048
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
187 words
An expansion circuit for digital signals, said expansion circuit being applied with a digital signal whose data has been compressed in such a manner that a predetermined number of bits are cut off from a plurality of bits forming said digital signal, to expand said compressed data, said expansion circuit comprising: bit adding means (9, 43) applied with said compressed digital signal for adding one or more bits to said compressed digital signal at the position following the least significant bit of said compressed digital signal; judging means (10, 14) applied with said compressed digital signal for judging the number of bits having been cut off in compressing said data, to supply said bit adding means (9, 43) with information with respect to the number of bits to be added; and adding means (30, 31; 26; 46) applied with said information with respect to the number of bits to be added, for giving correction data to said one or more added bits, said correctiondata being a numerical value which is about one half the largest one of numerical values expressed by said one or more added bits.
Claim 2
Dependent Claim
187 words
An expansion circuit for digital signals, said expansion circuit being applied with a digital signal whose data has been compressed in such a manner that a predetermined number of bits are cut off from a plurality of bits forming said digital signal, to expand said compressed data, said expansion circuit comprising: bit adding means (9, 43) applied with said compressed digital signal for adding one or more bits to said compressed digital signal at the position following the least significant bit of said compressed digital signal; judging means (10, 14) applied with said compressed digital signal for judging the number of bits having been cut off in compressing said data, to supply said bit adding means (9, 43) with information with respect to the number of bits to be added; and adding means (30, 31; 26; 46) applied with said information with respect to the number of bits to be added, for giving correction data to said one or more added bits, said correctiondata being a numerical value which is about one half the largest one of numerical values expressed by said one or more added bits.
Claim 3
Dependent Claim
208 words
An expansion circuit for digital signals, said expansion circuit being applied with a digital signal whose data has been compressed in such a manner that a predetermined number of bits are cut off from a plurality of bits forming said digital signal, to expand said compressed data, said expansion circuit comprising: a shift register (9) applied with said compressed digital signal for shifting a plurality of bits forming said compressed digital signal to add one or more bits to said shifted bits at the position following the least significant bit of said shifted bits; judging means (10) applied with said compressed digital signal for judging the number of bits having been cut off in compressing said data, to supply said shift register (9) with information with respect to the number of bits, by which said compressed digital signal is shifted in said shift register (9); and adding means (30, 31; 26) applied with said information from said judging means (10), for giving correction data to said one or more added bits, said correction data being a numerical value which is about one half the largest one of numerical values expressed by one or more bits, by which said compressed digital signal is shifted in said shift register (9).
Claim 4
Dependent Claim
208 words
An expansion circuit for digital signals, said expansion circuit being applied with a digital signal whose data has been compressed in such a manner that a predetermined number of bits are cut off from a plurality of bits forming said digital signal, to expand said compressed data, said expansion circuit comprising: a shift register (9) applied with said compressed digital signal for shifting a plurality of bits forming said compressed digital signal to add one or more bits to said shifted bits at the position following the least significant bit of said shifted bits; judging means (10) applied with said compressed digital signal for judging the number of bits having been cut off in compressing said data, to supply said shift register (9) with information with respect to the number of bits, by which said compressed digital signal is shifted in said shift register (9); and adding means (30, 31; 26) applied with said information from said judging means (10), for giving correction data to said one or more added bits, said correction data being a numerical value which is about one half the largest one of numerical values expressed by one or more bits, by which said compressed digital signal is shifted in said shift register (9).
Claim 5
Dependent Claim
49 words
An expansion circuit according to Claim 2, wherein said judging means includes counter means (10) for changing its count content in response to clock pulses, to generate an output signal when its count content has changed by a predetermined number corresponding to the number of bits to be added.
Claim 6
Dependent Claim
39 words
An expansion circuit according to Claim 3, wherein said adding means includes memory means (31) storing said correction data, and responsive to a signal representing the number of bits having been cut off, for outputting the corresponding correction data.
References Cited (Backward Citations)
No citation records indexed.
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