A differential signal receiver

Claim 2

A differential signal receiver comprising a differential amplifier (15,16,17,18,23) for comparing differential voltages of differential input signals (Vi l ,Vi 2 ) with a threshold voltage (Va, Vb) to provide logical output signals (Vo, Vo ) characterised in that the differential signal receiver also includes at least a first emitter follower (19,21) and at least a first impedance means (5,6,7,8,9,10) the output of the first emitter follower (19,21) being superimposed through the first impedance means (5,6,7,8,9,10) on to one of the differential input signals (Vi 1 ,Vi 2 ) whereby the threshold voltage (Va,Vb) is varied by controlling an input voltage (Ve,Vf) applied to the first emitter follower (19,21).

Claim 3

A variable-threshold differential signal receiver according to claim 1, wherein the differential amplifier comprises a first NPN transistor (17), a second NPN transistor (18), a first current source (23) connected between the emitters of the NPN transistors and a low voltage power supply line (VEE), a first resistor (15) connected between the collector of the first NPN transistor (17) and a high voltage power supply line (V CC ), a second resistor (16) connected between the collector of the second NPN transistor (18) and the high voltage power supply line (V CC ), and at least one output terminal (3,4) connected to the collector of the first NPN transistor (17) or to the second NPN transistor (18), the output terminal (3,4) being arranged to provide the logical output signals (Vo,Vo).

Claim 4

A variable-threshold differential signal receiver according to claim 2, wherein the first emitter follower comprises a third NPN transistor (19) having its collector connected to the high voltage power supply line (V CC ), its emitter connected through a third resistor (6) to the base of the first NPN transistor (17) and its base arranged to receive a first control voltage (Ve).

Claim 5

A variable threshold differential signal receiver according to claim 3, wherein the first impedance means comprises the third resistor (6), a fourth resistor (5) connected between a first input terminal (1) of the receiver and the base of the first NPN transistor (17), and a fifth resistor (7) connected between the base of the first NPN transistor (17) and the low-voltage power supply line (VEE).

Claim 6

A variable-threshold differential signal receiver according to claim 2, 3 or 4, further comprising a second emitter follower and a second impedance means, the second emitter follower comprising a fourth NPN transistor (21) having its collector connected to the high-voltage power supply line (V CC ), its emitter connected through a sixth resistor (9), to the base of the second NPN transistor (18), and its base adapted to receive a second control voltage (14), the second impedance means comprising the sixth resistor (9), a seventh resistor (8) connected between a second input terminal (2) of the receiver and the base of the second NPN transistor (18), and an eighth resistor (10) connected between the base of the second NPN transistor (18) and the low-voltage power supply line (VEE).

Claim 7

A variable threshold differential signal receiver according to claim 5, further comprising (Figure 3): a fifth NPN transistor (20) having its collector connected to the high-voltage power supply line (V CC ). and its emitter connected to the emitter of the third NPN transistor (19), a ninth resistor (11) and a tenth resistor (12) connected in series between the high voltage power supply line (V cc ) and the base of the third NPN transistor (19); a second current source (24) being connected between the base of the third NPN transistor (19) and the low voltage power supply line (VEE); a sixth NPN transistor (21) having its collector connected to the high voltage power supply line (V CC ) and its emitter connected to the emitter of the fourth NPN transistor (22); an eleventh resistor (13) and a twelfth resistor (14) connected in series between the high voltage power supply line (V CC ) and the base of the fourth NPN transistor (22); and, a third current source (25) connected between the base of the fourth NPN transistor (22) and the low voltage power supply line (V EE ); the base of the fifth NPN transistor (20) being connected to a connecting point between the eleventh (13) and twelfth (14) resistors and the base of the sixth NPN transistor (21) being connected to a connecting point between the ninth (11) and tenth (12) resistors, whereby by varying the current flowing through the second current source (24) or through the third current source (25), the threshold voltage (Va,Vb) is controlled.

Claim 8

A variable threshold differential signal receiver according to claim 5, further comprising (Figure 4a): a fifth NPN transistor (20) having its collector connected to the high voltage power supply line (V CC ) and its emitter connected to the emitter of the third NPN transistor (19); aninth resistor (11) and a tenth resistor (12) connected in series between the high voltage power supply line (V CC ) and the base of the third NPN transistor (19); a sixth NPN transistor (21) having its collector connected to the high voltage power supply line (V CC ) and its emitter connected to the emitter of the fourth NPN transistor (22); an eleventh resistor (13) and a twelfth resistor (14) connected in series between the high voltage power supply line (V cc ) and the base of the fourth NPN transistor (22); a first current switch (CS) connected between the base of the third NPN transistor (19) and the- low voltage power supply line (VEE); and, a second current source (242,251) connected between the base of the fourth NPN transistor (22) and the low voltage power supply line (VEE).

Claim 9

A variable threshold differential signal receiver according to claim 7, wherein the first current switch (CS) comprises emitter-coupled seventh (102) and eighth (101) NPN transistors and a third current source (241) connected between the emitters of the seventh (102) and eighth (101) NPN transistors and the low voltage power supply line (VEE), the collector of the seventh NPN (102) transistor being connected to the base of the third NPN transistor (19}, the collector of the eighth (101) NPN transistor being connected to the high voltage power supply line (V CC ), the base of the seventh (102) NPN transistor being arranged to receive a reference voltage (V BB ) and the base of the eighth (101) NPN transistor being arranged to receive a first control voltage (V CONT ).

Claim 10

A variable threshold differential signal receiver according to claim 8, further comprising a second current switch (CS' Figure 4B) connected between the base of the fourth NPN transistor (22) and the low-voltage power supply line (VEE), the second current switch (CS') comprising emitter coupled ninth (103) and tenth (104) NPN transistors and the second current source (242) being connected between the emitters of the ninth (103) and tenth (104) NPN transistors and the low voltage power supply line (VEE), the collector of the ninth NPN transistor (103) being connected to the base of the fourth NPN transistor (22), the collector of the tenth NPN transistor (104) being connected to the high voltage power supply line (V CC ) the base of the ninth NPN transistor (103) being arranged to receive a reference voltage (V BB ) and the base of the tenth NPN transistor (104) being arranged to receive a second control-voltage (VCONT).

Claim 11

A variable threshold differential signal receiver according to claim 5, wherein the first resistor comprises at least two resistors (15a,15b, Figure 6) and the second resistor comprises at least two resistors (16a,16b), the base of the third NPN transistor (20) being connected to a connecting point between the at least two resistors (16a,16b) forming the second resistor (16) and the base of the fourth NPN transistor (22) being connected to a connecting point between the at least two resistors (15a, 15b) of the first resistor (15).

Claim 12

A variable threshold differential signal receiver according to claim 5, further comprising: a fifth NPN transistor (20, Figure 7) having its collector connected to the high voltage power supply line (V cc ), and its emitter connected to the emitter of the third NPN transistor (19); a ninth resistor (11) and a tenth resistor (12) connected in series between the high voltage power supply line (V CC ) and the base of the third NPN transistor (19); a sixth NPN transistor (21) having its collector connected to the high voltage power supply line (V CC ) and its emitter connected to the emitter of the fourth NPN transistor (22); a first current switch (CS) connected between the base of the third NPN transistor (19) and the low voltage power supply line (VEE); and, said first resistor (15) comprising at least two resistors (15a, 15b) and the second resistor (16) comprising at least two resistors (16a,16b) the base of the fifth NPN transistor (20) being connected to a connecting point between the at least two resistors (16a, 16b) of the second resistor (16) and the base of the fourth NPN transistor (20) being connected to a connecting point between the at least two resistors (15a, 15b) of the first resistor (15).