Patent US5751131A successfully refreshed from Google Patents.
Patent EP0099983A2 successfully refreshed from Google Patents.
EP0099983A2
Expired / Lapsed
EP
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1983-06-14
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Granted: —
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Expires: 2003-06-14
Abstract
Abstract A memory device of the invention has a P type substrate, a first drain area (29 2 ) of N type formed in the substrate, a second drain area (29 3 ) of N type formed in the substrate close to the first drain area (29 2 ), and a source area (29,) of N + type formed around the first and second drain areas (29 2 , 29 3 ) so that the source area (29,) continuously surrounds the drain areas (29 2 , 29 3 ) from three sides, e.g., the right, left and top sides of these areas. The combination of the closed arrangement of the drain areas (29 2 , 29 3 ) and the surrounding arrangement of the source area (29,) decreases minority carriers generated around the drain areas (29 2 , 29 3 ) and prevents unbalanced carrier absorption of the drain areas (29 2 , 29 3 ), thereby suppressing the occurrence of a soft error.
Inventors
- 👤 Shoji Ariizumi
- 👤 Makoto Segawa
- 👤 Fujio Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 13:29
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/15; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
176 words
A semiconductor memory device including memory cells which have bistable flip-flop circuits formed of cross-coupled transistors (Ql, Q2), characterized by: a semiconductor substrate (10); a first drain area (29 2 ) of one (Ql) of said cross-coupled transistors formed at a given position on said substrate, said first drain area (29 2 ) being of a first conductivity type (N); a second drain area (29 3 ) of another (Q2) of said cross-coupled transistors being so formed in said substrate that said second drain area (29 3 ) is arranged close to said first drain area (292), said second drain area (29 3 ) being of said first conductivity type (N); and a source area (291) of said cross-coupled transistors (Ql, Q2) being so formed in said substrate that said source area (29 . ) surrounds said first and second drain areas (29 2 , 29 3 ) from three sides of a location in which said cross-coupled transistors (Ql, Q2) are formed, said source area (29 1 ) being of said first conductivity type (N).
Claim 2
Dependent Claim
176 words
A semiconductor memory device including memory cells which have bistable flip-flop circuits formed of cross-coupled transistors (Ql, Q2), characterized by: a semiconductor substrate (10); a first drain area (29 2 ) of one (Ql) of said cross-coupled transistors formed at a given position on said substrate, said first drain area (29 2 ) being of a first conductivity type (N); a second drain area (29 3 ) of another (Q2) of said cross-coupled transistors being so formed in said substrate that said second drain area (29 3 ) is arranged close to said first drain area (292), said second drain area (29 3 ) being of said first conductivity type (N); and a source area (291) of said cross-coupled transistors (Ql, Q2) being so formed in said substrate that said source area (29 . ) surrounds said first and second drain areas (29 2 , 29 3 ) from three sides of a location in which said cross-coupled transistors (Ql, Q2) are formed, said source area (29 1 ) being of said first conductivity type (N).
Claim 3
Dependent Claim
91 words
The device of claim 1, characterized in that each of said cross-coupled transistors (Ql, Q2) has a gate region (Gl or G2) and a gate electrode pattern (24 or 25) formed on said gate region and, at a location near the overlap area of said gate electrode pattern (e.g., 24) and said gate region (e.g., Gl), both said gate region (Gl) and said gate electrode pattern (24) have straight figures, and the straight portion of said gate region (Gl) meets that of said gate electrode pattern (24) at substantially right angles.
Claim 4
Dependent Claim
73 words
The device of claim 1 or 2, characterized in that said bistable flip-flop circuit includes a pair of load resistor elements (Rl, R2) respectively coupled to said first and second drain areas (29 2 , 29 3 ), and a first resistor pattern (32) for forming one (R1) of said load resistor elements is arranged substantially parallel to a second resistor pattern (31) for forming the other (R2) of said load resistor elements.
Claim 5
Dependent Claim
26 words
The device of claim 3, characterized in that each of said first and second resistor patterns (32, 31) has a straight figure along their parallel arrangement.
Claim 6
Independent Claim
148 words
The device of any one of claims 1 to 4, characterized in that said memory device has a pair of data lines (DL, DL) and a word line (WL) for each memory cell, and each of said memory cells includes: a first transfer-gate transistor (Q3) coupled between one (DL) of said data lines and said first drain area (29 2 ), said first transfer-gate transistor (Q3) being arranged along the running direction of said one data line (DL) ; and a second transfer-gate transistor (Q4) coupled between the other (DL) of said data lines and said second drain area (293), said second transfer-gate transistor (Q4) being arranged along the running direction of said other data line (DL), and characterized in that a gate electrode of each of said first and second transfer-gate transistors (Q3, Q4) is formed by a wiring pattern (26) coupled to said word line (WL).
Claim 7
Dependent Claim
35 words
The device of claim 5, characterized in that both said wiring pattern (26) and said word line (WL) are made of a polysilicon, and said word line (WL) is formed over said wiring pattern (26).
Claim 8
Independent Claim
43 words
The device of any one of claims 1 to 6, characterized in that said substrate (10) has a second conductivity type (P) well (10W) and said first and second drain areas (29 2 , 29 3 ) are formed in said well (10W).
Claim 9
Independent Claim
31 words
The device of any one of claims 3 to 7, characterized in that said first and second resistor patterns (32, 31) are respectively formed over said gate electrode patterns (25, 24).
Claim 10
Dependent Claim
21 words
The device of claim 8, characterized in that said first and second resistor patterns (32, 31) are made of a polysilicon.
Claim 11
Independent Claim
58 words
The device of any one of claims 3 to 9, characterized in that said source area (29 1 ) is coupled to a first power line (27) being made of a polysilicon, and said first and second resistor patterns (32, 31) are coupled to a second power line (33) which is formed over said first power line (27).
References Cited (Backward Citations)
No citation records indexed.
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