EP0099544A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Method for forming conductive lines and via studs on LSI carrier substrates
Assignee: International Business Machines Corp
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Filing: 1983-07-13
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Granted: —
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Expires: 2003-07-13
Abstract
Abstract A multilevel metallurgy is formed on a dielectric body, particularly a multilayer ceramic (MLC) body (10). The interconnection lines (22) and via studs (26) are formed as an integral structure from a blanket metal layer thus eliminating the interface beween the via pad and via stud. A second level of interconnections (25) can be formed on top of said first interconnection level.
Inventors
- 👤 Paul Martin Schaible
- 👤 John Suierveld
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 17:50
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/46; H05K3/4644; H05K3/4647; H05K3/4602; H05K3/4605; H10; H10W; H10W70/00; H10W70/01; H10W70/05; H10W70/095; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/685; H05K1/00; H05K1/02; H05K1/03; H05K1/0306; H05K2201/00; H05K2201/01; H05K2201/0137; H05K2201/0179; H05K2203/00; H05K2203/03; H05K2203/0369; H05K2203/07; H05K2203/0703; H05K2203/0733; H05K3/02; H05K3/06; H05K3/061; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
123 words
A method of fabricating an electrical interconnection package with a dielectric body (10) having an interconnection pattern (16) and vias (14) therein, the vias extending from said interconnection pattern and forming a planar surface with said dielectric body, characterized by the following steps: depositing a blanket layer (20) of conductive material on said planar surface, delineating said layer of conductive material into a circuit pattern (32) connected to said vias, forming an etch mask (38) on the surface of said circuit pattern to define the area where via studs (33) are to be formed, etching unmasked areas of said circuit pattern to reduce the thickness of the circuit pattern and to form via studs, and depositing dielectric material (50) on said dielectric body.
Claim 2
Independent Claim
123 words
A method of fabricating an electrical interconnection package with a dielectric body (10) having an interconnection pattern (16) and vias (14) therein, the vias extending from said interconnection pattern and forming a planar surface with said dielectric body, characterized by the following steps: depositing a blanket layer (20) of conductive material on said planar surface, delineating said layer of conductive material into a circuit pattern (32) connected to said vias, forming an etch mask (38) on the surface of said circuit pattern to define the area where via studs (33) are to be formed, etching unmasked areas of said circuit pattern to reduce the thickness of the circuit pattern and to form via studs, and depositing dielectric material (50) on said dielectric body.
Claim 3
Dependent Claim
19 words
The method of claim 1, wherein a second level of interconnections (25) is formed on said dielectric material (10).
Claim 4
Dependent Claim
30 words
The method of claim 2, wherein the minimum via stud (33) spacing of said circuit pattern (32) is smaller than that of said vias (14) in said dielectric body (10).
Claim 5
Dependent Claim
59 words
The method of claim 3, wherein the step of forming an etch mask on the surface of said circuit pattern (32) includes the steps of applying a photoresist film (36) on said dielectric body, forming openings (40) in the photoresist film where said via studs (33) are to be formed, and depositing a masking material (38) in said openings.
Claim 6
Dependent Claim
19 words
The method of claim 4, wherein said photoresist film (36) is removed carrying away the overlying masking material (38).
Claim 7
Dependent Claim
20 words
The method of claim 3, wherein said dielectric body (10) is a ceramic body having multiple layers of interconnections (16).
Claim 8
Dependent Claim
35 words
The method of claim 1, wherein said blanket layer (20) comprises top and bottom chromium layers, 0 each preferably about 0,8 µm (800 A) thick, and a center copper layer, preferably about 18 µm thick.
Claim 9
Independent Claim
26 words
The method of claims 1 and 4, wherein said masking material (38) is magnesium oxide and said etching step is carried out using reactive ion etching.
Claim 10
Independent Claim
23 words
The method of claims 7 and 8, wherein said blanket layer (20) thickness in the unmasked areas is reduced to about 3 µm.
Claim 11
Dependent Claim
23 words
The method of claim 1, wherein said delineating step is carried out by etching using said dielectric body (10) as an etch stop.
References Cited (Backward Citations)
US3726002A
Cited
US4132586A
Cited
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