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EP0099473B1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Integrated combined dynamic ram and ros

Assignee: International Business Machines Corp
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Filing: 1983-06-16
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Granted: 1990-03-14
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Expires: 2003-06-16
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Abstract

No abstract record available.

Inventors

  • 👤 Harish N. Kotecha

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-09 03:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/005; G11C17/00; G11C17/08; G11C17/10; G11C17/12; H; H10; H10B; H10B12/00; H10B12/30; H10B20/00

Claims Analysis

Total Claims: 1
Claim 1
Independent Claim 332 words
Integrated combined read-only storage and read/write random access semiconductor memory comprising memory cells in rows and columns and common peripheral circuits on a chip, whereby each cell comprises a first FET device, a second FET device, and a charge-storage element, whereby said charge-storage element is shared for both read-only storage and read/write random access memory operation, characterized by said first FET device (222) having its source/ drain path connected between a column line (224) and a cell node (226) and having a selectively programmable gate (228) connected to a first word line (230), for providing read-only storage for a first binary bit by conducting current between said column line and said cell node in response to a signal on said first word line when said selectively programmable gate has a first binary state and by blocking current between said column line and said cell node when said selectively programmable gate has a second binary state; said charge storage element (232) connected between said cell node (226) and a constant potential node (234), for dynamically storing a charge representing a binary bit; said second FET device (236) having its source/ drain path connected between a bit sensing line (238) and said cell node (226) and having a gate (240) connected to a second word line (242), for providing read/write random access memory for a second binary bit by conducting current between said bit sensing line and said charge storage element at said cell node in response to a signal on said second word line; said first FET device (222) being read by passing a charge from said bit sense line through said second FET device (236) to said charge storage element during a first stage, selectively discharging said storage element through said first FET device to said column line during a second stage if said selectively programmable gate of said first FET device has said first binary state, and then pulsing said first word line to sense whether said storage element is discharged.

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