Patent EP0099189A2 successfully refreshed from Google Patents.
EP0099189A2
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EP
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High speed CPU/sequencer for video games
Assignee: Bally Manufacturing Corp
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Filing: 1983-06-16
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Granted: —
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Expires: 2003-06-16
Abstract
Abstract A high speed CPU/sequencer for use in a video game provides multi-channel binary output for display control purposes. The CPU/sequencer includes a macro-section (16) that is user programmable with macro-instructions and a micro-section (18) that is user programmable with micro-instructions. The CPU/sequencer is responsive to display information provided by a game microprocessor during a brief handshake period and carries out display computations independently of the game microprocessor, at higher speed, and using larger binary data words.
Inventors
- 👤 John Jacob Pasierb, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 17:24
CPC Classifications
A; A63; A63F; A63F13/00; A63F13/50; G; G09; G09G; G09G5/00; G09G5/42
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
270 words
A high speed CPU/sequencer for use in a video game generating video display data, the game including a raster scan video display and video display circuitry having a memory for controlling said video display, and also including a microprocessor which generates the video display data in response to player controllable inputs, the microprocessor having a predetermined cycle time for retrieving information from the memory, said CPU/sequencer comprising; digital clock means responsive to the display circuitry for generating signals including digital clock signals, said digital clock signals having a period substantially shorter than said microprocessor cycle time; macro-sequencer means including a memory containing user programmable macro-instructions in a predetermined sequence and read out means for reading respective groups of sequential said macro-instructions in response to digital signals, said read out means being responsive to said signals from said digital clock means; and micro-sequencer means responsive to the video display data and said macro-instructions including a memory containing a plurality of predetermined sequences of user programmable micro-instructions, means for executing said micro-instructions in response to said digital clock signals, and a plurality of output channels for carrying binary data between the C P U/ sequencer and the video display circuitry and said macro-sequencer means; wherein one of said plurality of predetermined sequences of micro-instructions is selected and executed in response to the reading of one of said macro-instructions by said macro-sequencer means, each micro-instruction of said sequence, when executed in response to said digital clock signals, 'determines the binary data carried on said plurality of output channels, and said binary data controls said sequential reading of said macro-instructions by said readout means.
Claim 2
Dependent Claim
270 words
A high speed CPU/sequencer for use in a video game generating video display data, the game including a raster scan video display and video display circuitry having a memory for controlling said video display, and also including a microprocessor which generates the video display data in response to player controllable inputs, the microprocessor having a predetermined cycle time for retrieving information from the memory, said CPU/sequencer comprising; digital clock means responsive to the display circuitry for generating signals including digital clock signals, said digital clock signals having a period substantially shorter than said microprocessor cycle time; macro-sequencer means including a memory containing user programmable macro-instructions in a predetermined sequence and read out means for reading respective groups of sequential said macro-instructions in response to digital signals, said read out means being responsive to said signals from said digital clock means; and micro-sequencer means responsive to the video display data and said macro-instructions including a memory containing a plurality of predetermined sequences of user programmable micro-instructions, means for executing said micro-instructions in response to said digital clock signals, and a plurality of output channels for carrying binary data between the C P U/ sequencer and the video display circuitry and said macro-sequencer means; wherein one of said plurality of predetermined sequences of micro-instructions is selected and executed in response to the reading of one of said macro-instructions by said macro-sequencer means, each micro-instruction of said sequence, when executed in response to said digital clock signals, 'determines the binary data carried on said plurality of output channels, and said binary data controls said sequential reading of said macro-instructions by said readout means.
Claim 3
Dependent Claim
93 words
A high speed CPU/sequencer according to Claim 1 wherein said micro-sequencer means includes logic means for responding to at least one combination of said binary data on said plurality of output channels by transmitting logic signals to said macro-sequencer means wherein said macro-sequencer means responds to said logic signals by jumping from at least one first specified macro-instruction after reading said macro-instruction to at least one second specified macro-instruction not in sequence with said first specified macro-instruction and after said jumping continues reading said macro-instructions in a sequence beginning'with said second specified macro-instruction.
Claim 4
Dependent Claim
23 words
A high speed CPU/sequencer according to Claim 2 wherein at least one of said logic signals is conditional upon said video display data.
Claim 5
Dependent Claim
25 words
A high speed CPU/sequencer according to Claim 1 wherein said digital clock means includes disabling means and enabling means responsive to the video display circuitry.
Claim 6
Dependent Claim
58 words
A high speed CPU/sequancer according to Claim 1 wherein the memory in said macro-sequencer means contains an initial macro-instruction and the memory in said micro-sequencer means contains an initial micro-instruction and said digital clock means includes timing/reset means responsive to said video display circuitry for setting said macro-sequencer and micro-sequencer to their respective initial macro- and micro- instructions.
Claim 7
Dependent Claim
26 words
A high speed CPU/sequencer according to Claim 1 further comprising storage means shared with the video display circuitry for receiving and storing said video display data.
Claim 8
Dependent Claim
53 words
A high speed CPU/sequencer according to any of Claims 1 to 6 further comprising arithmetic means for performing arithmetic and logical operations upon said video display data in response to said binary data on said plurality of output channels and for transmitting the results of said arithmetic and logical operations to said micro-sequencer.
Claim 9
Dependent Claim
30 words
A high speed CPU/sequencer according to Claim 7 wherein said micro-sequencer combines said results of said arithmetic and logical operations with said binary data on said plurality of output channels.
Claim 10
Dependent Claim
16 words
A high speed CPU/sequencer according to Claim 7 wherein said memory containing macro-instructions is a ROM.
Claim 11
Dependent Claim
18 words
A high speed CPU/sequencer according to Claim 7 wherein said memory containing sequences of micro-instructions is a ROM.
Claim 12
Dependent Claim
34 words
A high speed CPU/sequencer according to Claim 10 wherein said ROM comprises a plurality of Fairchild programmable 93448 ROM's ganged together to provide micro- instructi ' ons having more than 8 bit word length.
Claim 13
Dependent Claim
21 words
A high speed CPU/sequencer according to Claim 7 wherein the number of output channels in said plurality is greater than 16.
Claim 14
Dependent Claim
23 words
A high speed CPU/sequencer according to Claim 7 wherein said micro-sequencer executes said micro-instructions at substantially the rate of said digital clock signals.
Claim 15
Dependent Claim
30 words
A high speed CPU/sequencer according to Claim 13 wherein the binary data on said plurality of output channels includes said micro-instructions and said results of said arithmetic and logical operations.
Claim 16
Dependent Claim
32 words
A high speed CPU/sequencer according to Claim 7 wherein said binary data on said plurality of output channels are adapted to control enable and read/write inputs of memory in said display circuitry.
Claim 17
Dependent Claim
37 words
A high speed CPU/sequencer according to Claim 7 wherein said binary data on said plurality of output channels is adapted to control enable and input selection inputs of a multiplexer in the display circuitry of the game.
Claim 18
Dependent Claim
36 words
A high speed CPU/sequencer according to Claim 7 wherein said micro-sequencer means further includes at least one latch such that said data on said plurality of output channels controls enable and clock inputs of said latch.
Claim 19
Dependent Claim
224 words
A high speed CPU/sequencer for use in a video game generating video display data, the game having a raster scan video display comprised of parallel lines, and having video display circuitry for controlling said video display, the game also including a microprocessor which generates the video display data, the microprocessor having a basic clock rate and cycle time, said high speed CPU/sequencer comprising: micro-system means for performing digital arithmetic and logical operations upon the video display data in times substantially less than the microprocessor cycle time and for generating sequences of digital output signals on a plurality of simultaneously actuatable output channels responsive to said digital operations, said sequences of signals being adapted to control memory, switching circuits, and logic gates in the video display circuitry; and macro-system means for designating to said micro-system means groups of at least two of said digital operations - to be performed sequentially, such designations being made in response to said video display data and said digital output signals, said macro-system means initiating its operation upon receipt of stimuli from said display circuitry and being adapted to operate independently of the timing of the raster scan video display to enable the video display circuitry to control at least one line of the raster scan display in response to said stimuli and independently of the operation of said CPU/sequencer.
Claim 20
Dependent Claim
224 words
A high speed CPU/sequencer for use in a video game generating video display data, the game having a raster scan video display comprised of parallel lines, and having video display circuitry for controlling said video display, the game also including a microprocessor which generates the video display data, the microprocessor having a basic clock rate and cycle time, said high speed CPU/sequencer comprising: micro-system means for performing digital arithmetic and logical operations upon the video display data in times substantially less than the microprocessor cycle time and for generating sequences of digital output signals on a plurality of simultaneously actuatable output channels responsive to said digital operations, said sequences of signals being adapted to control memory, switching circuits, and logic gates in the video display circuitry; and macro-system means for designating to said micro-system means groups of at least two of said digital operations - to be performed sequentially, such designations being made in response to said video display data and said digital output signals, said macro-system means initiating its operation upon receipt of stimuli from said display circuitry and being adapted to operate independently of the timing of the raster scan video display to enable the video display circuitry to control at least one line of the raster scan display in response to said stimuli and independently of the operation of said CPU/sequencer.
Claim 21
Dependent Claim
26 words
A high speed CPU/sequencer according to Claim 18 further comprising communication and memory means for receiving and storing said video display data for said micro-system means.
Claim 22
Dependent Claim
29 words
A high speed CPU/sequencer according to Claim 19 wherein said communication and memory means includes a shared memory accessible to said microprocessor, said display circuitry, and said micro-system means.
Claim 23
Dependent Claim
62 words
A high speed CPU/sequencer according to Claim 20, said shared memory comprises a plurality of RAM's wherein said microprocessor writes into fewer than all of said RAM's at any one time, and said micro-system means reads all of said RAM's substantially simultaneously, thereby providing for substantially parallel transfer of data to said micro-system on more channels than are available to said microprocessor.
Claim 24
Dependent Claim
22 words
A high speed CPU/sequencer according to Claim 21 wherein said shared memory comprises four 93442 RAMs addressed by said microprocessor in pairs.
Claim 25
Dependent Claim
208 words
In a video game having a display monitor and processor means for determining display positions of objects on said monitor screen in response to player- controllable inputs to said processor means, said processor means outputting data signals during a handshake interval designating said objects and their associated display positions, a high speed CPU/sequencer video display system comprising: video control means for timing and control of any of the sweep, color, intensity, and blanking of said display; and CPU/sequencer means with associated memory and binary data channels for providing video display signals in response to the data signals, said CPU/sequencer means comprising logic means, a macro-section programmable by a user with macro-instructions and a micro-section programmable by a user with micro-instructions, the micro-instructions being executed at a rate greater than 7.5 instructions per microsecond, and each said micro-instruction controlling the state of more than 8 said binary data channels; wherein said video control means receives and is responsive to said video display signals, each of said macro-instructions is executed by a sequence of micro-instructions, said macro-instructions are executed in sequences dependent upon said data signals, and the binary data on said binary data channels enables said logic means to provide said video display signals to said video control means.
Claim 26
Dependent Claim
208 words
In a video game having a display monitor and processor means for determining display positions of objects on said monitor screen in response to player- controllable inputs to said processor means, said processor means outputting data signals during a handshake interval designating said objects and their associated display positions, a high speed CPU/sequencer video display system comprising: video control means for timing and control of any of the sweep, color, intensity, and blanking of said display; and CPU/sequencer means with associated memory and binary data channels for providing video display signals in response to the data signals, said CPU/sequencer means comprising logic means, a macro-section programmable by a user with macro-instructions and a micro-section programmable by a user with micro-instructions, the micro-instructions being executed at a rate greater than 7.5 instructions per microsecond, and each said micro-instruction controlling the state of more than 8 said binary data channels; wherein said video control means receives and is responsive to said video display signals, each of said macro-instructions is executed by a sequence of micro-instructions, said macro-instructions are executed in sequences dependent upon said data signals, and the binary data on said binary data channels enables said logic means to provide said video display signals to said video control means.
Claim 27
Dependent Claim
24 words
A high speed CPU/sequencer video display system in accordance with Claim 23 wherein each said micro-instruction controls the state of more than 20 channels.
References Cited (Backward Citations)
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