Patent US2403773A successfully refreshed from Google Patents.
Patent EP0098932A2 successfully refreshed from Google Patents.
EP0098932A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Repairable multi-level system for semiconductor device
Assignee: International Business Machines Corp
•
Filing: 1983-05-06
•
Granted: —
•
Expires: 2003-05-06
Abstract
Abstract @ A multi-level integrated circuit packaging system has a primary support frame (N), an array of secondary support frames (H) mounted in said primary support frame and an array of single chip carriers associated with each secondary support frame. An integrated circuit is encapsulated in each single chip carrier, which has an insulated wiring pattern with EC wells and delete lands (d). The secondary and primary support frames also have EC pads so that a change capability exists to any electrical signal path terminating on the chip.
Inventors
- 👤 Mario E. Ecker
- 👤 Leonard T. Olson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 20:10
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W40/00; H10W40/60; H10W40/611; H10W70/62; H10W70/641; H10W90/00; H10W90/401; H10W40/20; H10W40/231; H10W40/235; H10W40/625; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
261 words
A multi-level integrated packaging structure for supporting and electrically interconnecting a plurality of integrated circuit chips comprising: a primary planar support frame (N) having a primary array of spaced areas, a wiring pattern disposed on said primary planar support frame providing connection contacts, engineering change (EC) wiring channels and contacts in spaces on said primary array between said areas, a plurality of secondary planar support frames (H) equal in number to said areas defining said spaced primary array, said plurality of secondary planar support frames (H) being respectively positioned within said primary array, each of said secondary planar support frames having a secondary array of spaced areas (1, 2, 3; A, B, C), each of said secondary planar support frames containing a wiring pattern (K, L, M) providing connection contacts, engineering change wiring channels and contacts in spaces on said secondary array between areas, a plurality of substantially planar single chip carriers disposed on said secondary arrays, each of said chip carriers containing at least an integrated circuit chip and having an array of exposed connection contact means, and containing wiring for electrically interconnecting said integrated circuit chip to said array of exposed connection contacts on said same single chip carrier, first connection means for connecting each of said single chip carriers to predetermined connection contacts on said secondary planar support frames (H), and second connection means for connecting predetermined contacts of said secondary planar support frames (H) to predetermined connection contacts of said primary planar support frame (N) facilitating repair and replacement of single chip carriers and engineering wiring changes.
Claim 2
Dependent Claim
261 words
A multi-level integrated packaging structure for supporting and electrically interconnecting a plurality of integrated circuit chips comprising: a primary planar support frame (N) having a primary array of spaced areas, a wiring pattern disposed on said primary planar support frame providing connection contacts, engineering change (EC) wiring channels and contacts in spaces on said primary array between said areas, a plurality of secondary planar support frames (H) equal in number to said areas defining said spaced primary array, said plurality of secondary planar support frames (H) being respectively positioned within said primary array, each of said secondary planar support frames having a secondary array of spaced areas (1, 2, 3; A, B, C), each of said secondary planar support frames containing a wiring pattern (K, L, M) providing connection contacts, engineering change wiring channels and contacts in spaces on said secondary array between areas, a plurality of substantially planar single chip carriers disposed on said secondary arrays, each of said chip carriers containing at least an integrated circuit chip and having an array of exposed connection contact means, and containing wiring for electrically interconnecting said integrated circuit chip to said array of exposed connection contacts on said same single chip carrier, first connection means for connecting each of said single chip carriers to predetermined connection contacts on said secondary planar support frames (H), and second connection means for connecting predetermined contacts of said secondary planar support frames (H) to predetermined connection contacts of said primary planar support frame (N) facilitating repair and replacement of single chip carriers and engineering wiring changes.
Claim 3
Dependent Claim
161 words
An improved multi-level integrated packaging structure for supporting and electrically interconnecting a plurality of integrated circuit chips comprising: a tiered support structure having a primary support frame (N), a plurality of secondary planar support frames (H) mounted on said primary support frame, and a plurality of single chip carriers mounted on said secondary support planar frames, said primary support frame (N) and each of said secondary support frames (H) having a wiring pattern providing connection contacts, engineering changes wiring channels and contacts thereon, integrated circuit chips mounted on said single chip carriers, said chip carriers having exposed contact means (G) and wiring for electrically interconnecting said integrated circuit chip to said contact means, first connection means for connecting predetermined contacts of said single chip carriers to predetermined connection contacts on said secondary planar support frames (H), and second connection means for connecting predetermined contacts of said secondary planar support frames (H) to predetermined contacts of said primary planar support frame (N).
Claim 4
Dependent Claim
161 words
An improved multi-level integrated packaging structure for supporting and electrically interconnecting a plurality of integrated circuit chips comprising: a tiered support structure having a primary support frame (N), a plurality of secondary planar support frames (H) mounted on said primary support frame, and a plurality of single chip carriers mounted on said secondary support planar frames, said primary support frame (N) and each of said secondary support frames (H) having a wiring pattern providing connection contacts, engineering changes wiring channels and contacts thereon, integrated circuit chips mounted on said single chip carriers, said chip carriers having exposed contact means (G) and wiring for electrically interconnecting said integrated circuit chip to said contact means, first connection means for connecting predetermined contacts of said single chip carriers to predetermined connection contacts on said secondary planar support frames (H), and second connection means for connecting predetermined contacts of said secondary planar support frames (H) to predetermined contacts of said primary planar support frame (N).
Claim 5
Dependent Claim
63 words
The multi-level integrated packaging structure of claims 1 or 2, further comprising a printed circuit board and a first primary planar support frame with its associated multi-level integrated packaging structure mounted on one surface of said printed circuit board, and a second primary planar support frame with its associated multi-level integrated packaging structure mounted on an opposite surface of said printed circuit board.
Claim 6
Dependent Claim
37 words
The multi-level integrated packaging structure of claims 1 or 2, wherein said single chip carriers comprise a plurality of insulating layers containing metallic wiring pattern to interconnect said exposed contact means with contacts on said integrated chips.
Claim 7
Dependent Claim
62 words
The multi-level integrated packaging structure of claim 4, wherein said exposed connection contact means comprise at least one pair of contact wells (b, c) serially disposed with a fixed separation therebetween and wherein said wiring for electrically interconnecting said integrated circuit chip includes a land portion (d) positioned within said insulating layers and adapted to be cut to isolate said contact wells.
Claim 8
Dependent Claim
57 words
The multi-level integrated packaging structure of claim 5, wherein said first connection means comprises a series of protrusions (G) disposed on said secondary planar support frame (H) positioned beneath said contact wells, said contact wells having reflow attach wells to establish electrical continuity between said contact wells and said protrusions, said protrusions defining a chip-to-chip wiring pattern.
Claim 9
Dependent Claim
38 words
The multi-level integrated packaging structure of claim 6, wherein said connection contacts comprise a series of engineering pads (K) positioned on said secondary planar support frames (H), each of said engineering pads connected to a distinct protrusion (G).
Claim 10
Dependent Claim
39 words
The multi-level integrated packaging structure of claim 6, wherein said contacts on said secondary planar support frames (H) comprise a series of contact well pairs (L, M), said protrusions and said contact well pairs defining a multi-level wiring interface.
Claim 11
Dependent Claim
32 words
The multi-level integrated packaging structure of claims 1 or 2, wherein said single chip carriers comprise one or more leadless chip carriers, tape automated bond carriers, or passivated face bonded chip carriers.
Claim 12
Dependent Claim
55 words
The multi-level integrated packaging structure of claims 1 or 2, further comprising a notch scribed along one edge of said secondary support frame (H), said notch extending partially through a ceramic support layer of said secondary support frame wherein, when said ceramic support is broken along said notch, following processing, an interconnection wire is created.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.