Phase lock loop circuit

Claim 2

A phase lock loop circuit, comprising a voltage controlled oscillator (7) arranged to be controlled in dependence upon a phase error signal, a sweep signal generator (8) operable to generate a sweep signal (a), and means (11,9,5) operable to superimpose the sweep signal (a) on the phase error signal thereby to sweep the voltage controlled oscillator (7), having means (11) operable to suspend such sweeping of the voltage controlled oscillator (7) when phase lock is achieved, characterised in that the means (11) operable to suspend such sweeping are operable, upon achievement of phase lock, to maintain the superimposition, on the phase error signal, of the level of the sweep signal (a) immediately before such achievement.

Claim 3

A phase lock loop circuit as claimed in claim 1, comprising: an input terminal ( 1 ) for receiving a phase shift keying signal; a phase detector (2) connected to the input terminal (1), for synchronously detecting the phase shift keying signal on the basis of a recovered carrier signal; a baseband processing circuit (4) connected to the phase detector (2), for processing an output signal of the phase detector (2), and for providing the phase error signal and a decision signal (b) which indicates whether or not the loop is phase-locked; a sweep oscillator (8) for generating a sweep signal (a); a selector circuit (11) which is supplied with the decision signal (b) and the sweep signal (a), operable to suspend application of the sweep signal (a) to the loop when the decision signal (b) indicates that the loop is phase-locked but operable to maintain the application of the level of the sweep signal (a) just before the decision signal provided such indication; a coupling capacitor (9) connected to an output terminal of the selector circuit (11); an adder circuit (5) which is supplied with the output of the selector circuit (11) via the coupling capacitor (9) and which is supplied with the phase error signal, for adding the output of the selector circuit (11) to the phase error signal; and a voltage controlled oscillator (7) which is arranged to be supplied with the output of the adder circuit (5) via a loop filter (6), as a control signal, for generating the recovered carrier signal.

Claim 4

A phase lock loop circuit as claimed in claim 2, wherein the phase shift keying signal which is supplied to the input terminal is a 4-level PSK signal.

Claim 5

A phase lock loop circuit as claimed in claim 1, 2 or 3 wherein the sweep signal is a square wave signal.