Static type semiconductor memory device

Claim 1

A static-type semiconductor memory device comprising: first and second power supply terminals (V CC , V SS ); a plurality of word lines (WL 0 to WL n-1 ); a plurality of pairs of bit lines (BL 0 , BL 0 , ---); a plurality of load means (Q L0 , Q L0 ', ---), each connected to one of said bit lines and to said first power supply temrinal, for charging said bit lines; a plurality of static memory cells (C 00 , C 01 , ---) each connected to one of said word lines and to one pair of said bit lines; a row-addressing means (RB, RD) for selecting one of said word lines upon the receipt of row-address information; a column-addressing means (CB, CD) for selecting one of said bit line pairs upon the receipt of column-address information; a sense amplifier (SA) for amplifying the difference in potential between a pair of bit lines selected by said column-addressing means; an output buffer (OB), connected to the output of said sense amplifier, for maintaining and outputting a data output signal (D OUT ); a first clock signal-generating circuit (CK 1 ) for detecting the change of said row-address information and said column-address information and generating a first clock signal (CP1); a second clock signal-generating circuit (CK 2 ) for detecting the change of the potential of said word lines and generating a second clock signal (CP2); and a word driver (WD) for activating said row-addressing means, said word driver being set by the rise of said first clock signal and reset by the rise of said second clock signal.