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EP0097825A2
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EP
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Transistor amplifier with constant current source
Assignee: Hitachi Ltd
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Filing: 1983-05-30
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Granted: —
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Expires: 2003-05-30
Abstract
Abstract A transistor circuit is used as a signal amplifier which has almost no possibility of oscillation in an IC. The transistor circuit includes a cascade connection of differential amplifiers. Each of the amplifiers comprises a differential pair of bipolar transistors and an enhancement-type MOSFET as a constant current source. The MOSFET of each amplifier is connected in the common source mode, and the drain is connected to the emitters of the differential pair of bipolar transistors. The sources of all the MOSFETS are connected to a common ground-line.
Inventors
- 👤 Isao Fukushima
- 👤 Yasunori Kobori
- 👤 Hideo Nishijima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 00:48
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/4508; H03F3/45085; H03F3/34; H03F3/343; H03F3/345
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
92 words
A transistorcircuit, including a differential pair of transistors and a constant current source for said differential pair, characterized in that said differential pair of transistors is a pair of bipolar transistors (1 ,2) , and said constant current source is formed by a FET (68) having a drain, a source and a gate , said FET being connected in a common source mode , the drain of which FET is connected to emitters of said bipolar transistors (1 ,2), and the gate of which FET is connected to bias supply means (8).
Claim 2
Dependent Claim
92 words
A transistorcircuit, including a differential pair of transistors and a constant current source for said differential pair, characterized in that said differential pair of transistors is a pair of bipolar transistors (1 ,2) , and said constant current source is formed by a FET (68) having a drain, a source and a gate , said FET being connected in a common source mode , the drain of which FET is connected to emitters of said bipolar transistors (1 ,2), and the gate of which FET is connected to bias supply means (8).
Claim 3
Dependent Claim
20 words
A transistor circuit according to claim 1 , characterized in that said FET (68) is an enhancement type MOS FET.
Claim 4
Dependent Claim
115 words
A transistor circuit, including a cascade connection of differential pairs of trasistors and constant current sources for each of said differential pairs, characterized in that said differential pairs of transistors are pairs of bipolar transistors(1 ,2, 34, 35), and each of said constant current sources is formed by one of a first group of FETs(68,63), each of which FETs has a drain, a source and a gate and is connected to a common ground - line in a common source mode, the drain of each of which FETs is connected to the emitters of each of said differential pairs of bipolar transistors (1 ,2,34,35), and thegates of which FETs are connected to bias supply means.
Claim 5
Dependent Claim
115 words
A transistor circuit, including a cascade connection of differential pairs of trasistors and constant current sources for each of said differential pairs, characterized in that said differential pairs of transistors are pairs of bipolar transistors(1 ,2, 34, 35), and each of said constant current sources is formed by one of a first group of FETs(68,63), each of which FETs has a drain, a source and a gate and is connected to a common ground - line in a common source mode, the drain of each of which FETs is connected to the emitters of each of said differential pairs of bipolar transistors (1 ,2,34,35), and thegates of which FETs are connected to bias supply means.
Claim 6
Dependent Claim
172 words
A transistor circuit, including a cascade connection of differential pairs of bipolar trnsistors (1 ,2,34,35), emitter follower bipolar transistors (30,31) inserted between adjacent differential pairs ofbipolar transistors (1 2, 34, 35 ) to operate as buffers between said adjacent differential pairs and constant current sources for each of said differential pairs and said emitter follower bipolar transistors, characterized in that each of said constant current sources is formed by one of a first group and a second group of FETs (68,63,61 62), each of which FETs has a drain, a source and a gate , is connected to a common ground - line in a common source mode, and the gates of which FETs are connected to bias supply means, the drain of each of said first group of FETs being connected to the emitters of each of said differential pairs of bipolar transistors (1 2, 34, 35), and the drain of each said second group of FETs being connected to the emitter of each of said emitter follower bipolar transistors (30,31).
Claim 7
Dependent Claim
172 words
A transistor circuit, including a cascade connection of differential pairs of bipolar trnsistors (1 ,2,34,35), emitter follower bipolar transistors (30,31) inserted between adjacent differential pairs ofbipolar transistors (1 2, 34, 35 ) to operate as buffers between said adjacent differential pairs and constant current sources for each of said differential pairs and said emitter follower bipolar transistors, characterized in that each of said constant current sources is formed by one of a first group and a second group of FETs (68,63,61 62), each of which FETs has a drain, a source and a gate , is connected to a common ground - line in a common source mode, and the gates of which FETs are connected to bias supply means, the drain of each of said first group of FETs being connected to the emitters of each of said differential pairs of bipolar transistors (1 2, 34, 35), and the drain of each said second group of FETs being connected to the emitter of each of said emitter follower bipolar transistors (30,31).
Claim 8
Dependent Claim
21 words
A transistor circuit according to claim 3 or 4 , characterized in that said FETs are enhancement type MOS FETs .
References Cited (Backward Citations)
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