Method for manufacturing semiconductor devices

Claim 1

A method for manufacturing a semiconductor device, comprising the steps of: selectively forming, in a surface layer of a semiconductor substrate (31) of a first conductivity type, a plurality of high concentration buried layers (32 1 , 32 2 ) having a second conductivity type, and growing an epitaxial semiconductor layer (33) of the first conductivity type on an entire surface of said substrate; forming well regions (35 1 , 35 2 ) of the second conductivity type which extend from a surface of said epitaxial semiconductor layer (33) to said high concentration buried layers (32 1 , 32 2 ); selectively forming a field insulating film (41) on the surface of said epitaxial semiconductor layer so as to form first conductivity type element regions and second conductivity type element regions surrounded by said field insulating film (41); forming a thin insulating film (42) on surfaces of said element regions; selectively doping one of said second conductivity type element regions with a first conductivity type impurity so as to form a first conductivity-type active base region (43) of a bipolar transistor; forming gate electrodes (47 1 , 47 2 ) of MOS transistors interposed with said insulating film on said first conductivity type element regions and remaining ones of said second conductivity type element regions in which said active base region (43) is not formed, said gate electrodes comprising polysilicon layers which are doped with an impurity to have a low resistance; forming a second conductivity type emitter region (49) in said first conductivity type active base region; selectively doping a second conductivity type impurity so as to simultaneously form a second conductivity type collector contact region (53) of said bipolar transistor, and second conductivity type source and drain regions (54, 55) of said MOS transistors in said first conductivity type element region, said second conductivity type source and drain regions being self-aligned with said gate electrodes of said MOS transistors; and selectively doping a first conductivity type impurity so as to form an external base region (50) of the first conductivity type in said first conductivity type base region and first conductivity type source and drain regions (51, 52) of said MOS transistors in said remaining ones of said second conductivity type element regions, said first conductivity type source and drain regions being self-aligned with said gate electrodes (47 1 , 47 2 ) of said MOS transistors.

Claim 2

A method for manufacturing a semiconductor device, comprising the steps of: selectively forming, in a surface layer of a semiconductor substrate (31) of a first conductivity type, a plurality of high concentration buried layers (32 1 , 32 2 ) having a second conductivity type, and growing an epitaxial semiconductor layer (33) of the first conductivity type on an entire surface of said substrate; forming well regions (35 1 , 35 2 ) of the second conductivity type which extend from a surface of said epitaxial semiconductor layer (33) to said high concentration buried layers (32 1 , 32 2 ); selectively forming a field insulating film (41) on the surface of said epitaxial semiconductor layer so as to form first conductivity type element regions and second conductivity type element regions surrounded by said field insulating film (41); forming a thin insulating film (42) on surfaces of said element regions; selectively doping one of said second conductivity type element regions with a first conductivity type impurity so as to form a first conductivity-type active base region (43) of a bipolar transistor; forming gate electrodes (47 1 , 47 2 ) of MOS transistors interposed with said insulating film on said first conductivity type element regions and remaining ones of said second conductivity type element regions in which said active base region (43) is not formed, said gate electrodes comprising polysilicon layers which are doped with an impurity to have a low resistance; forming a second conductivity type emitter region (49) in said first conductivity type active base region; selectively doping a second conductivity type impurity so as to simultaneously form a second conductivity type collector contact region (53) of said bipolar transistor, and second conductivity type source and drain regions (54, 55) of said MOS transistors in said first conductivity type element region, said second conductivity type source and drain regions being self-aligned with said gate electrodes of said MOS transistors; and selectively doping a first conductivity type impurity so as to form an external base region (50) of the first conductivity type in said first conductivity type base region and first conductivity type source and drain regions (51, 52) of said MOS transistors in said remaining ones of said second conductivity type element regions, said first conductivity type source and drain regions being self-aligned with said gate electrodes (47 1 , 47 2 ) of said MOS transistors.

Claim 6

A method according to claims 1 to 4, characterized in that said gate electrodes (47,, 47 2 ) of said MOS transistors comprise gate electrodes which have a low resistance due to doping with phosphorus and arsenic.

Claim 7

A method according to claims 1 to 5, characterized in that among said gate electrodes (47 1 , 47 2 ) of said M OS transistors, said gate electrode (472) of said p-channel MOS transistor comprises a gate electrode which has a low resistance by doping with boron, and said gate electrode (47 1 ) of said n-channel MOS transistor comprises a gate electrode which has a low resistance due to doping with phosphorus and arsenic.

Claim 8

A method according to claims 3 to 6, characterized in that said emitter electrode (46) is doped with arsenic as the second conductivity type impurity.

Claim 9

A method according to claims 3 to 7, characterized in that a collector electrode comprising a polysilicon layer doped with the second conductivity-type impurity is formed, and said second conductivity type collector contact region (53) is formed using said collector electrode as a diffusion source in a similar manner to said second conductivity type emitter region (43) .

Claim 11

A method according to claims 8 and 9, characterized in that said collector electrode used as said diffusion source for forming said second conductivity type collector contact region (53) comprises, as said gate electrodes (47 1 , 47 2 ) of said MOS transistors, a polysilicon layer which has a low resistance due to doping with phosphorus or phosphorus and arsenic.

Claim 12

A method according to claims 1 to 10, characterized in that in the step for forming said gate electrodes (47 1 , 472 ) of said MOS transistors, polysilicon resistor whose resistance has been controlled by doping of an impurity is formed on said field insulating film (41).

Claim 14

A method according to claims 1 to 12, characterized in that in the step for forming said second conductivity type wells (35 1 , 35 2 ), second conductivity type high-concentration connecting regions (58 1 , 58 2 ) are formed which extend from surfaces of said second conductivity type.wells (35 1 , 35 2 ) to said second conductivity type high-concentration buried layers (32 1 , 32 2 ).

Claim 15

A method according to claims 1 to 13, characterized in that in the step-for forming said second conductivity type wells (35 1 , 35 2 ), a first conductivity type high-concentration impurity diffusion layer (59) surrounding the well (35 1 ) is formed in said first conductivity type epitaxial semiconductor layer (33), which extends from the surface of said first conductivity type epitaxial semiconductor layer (33) to said first conductivity type semiconductor substrate (31).