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EP0096176A2
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Method of logic simulation and logic simulation machine
Assignee: International Business Machines Corp
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Filing: 1983-03-30
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Granted: —
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Expires: 2003-03-30
Abstract
Abstract An improved logic simulation machine in which non-unitary delays of logic functions being simulated are permitted and in which the delay time can be made different for low-to-high and high-to-low transitions. A plurality of basic processors are interconnected with a control processor through an inter-processor switch. The logic functions being simulated are divided among the various basic processors. The control processor provides primary input data and communicates the results computed by the basic processors with other ones of the basic processors as needed. All of the basic processors and the control processor operate in variable length work cycles. The length of a work cycle is determined by a minimum work space value among all of the logic functions to be simulated, that is, a minimum time to a next successive transition in a simulated output among all of the simulated logic functions. Further, the presence of glitches in the simulated output is detected. The detected glitches are suppressed if their duration is less than the delay time of the logic function being simulated for a particular transition it is predicted to undergo.
Inventors
- 👤 Metthew Christopher Graf
- 👤 Robert Brewster Hitchcock, Sr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 13:18
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
65 words
A method for simulating logic operations comprising the steps of: determining a value of a simulated logic function output in each of a plurality of basic processors operating in time unison as a proposed output with a fixed constant delay for the logic function being simulated;and delaying said proposed output from a final output for a delay time specific to said logic function being simulated.
Claim 2
Independent Claim
65 words
A method for simulating logic operations comprising the steps of: determining a value of a simulated logic function output in each of a plurality of basic processors operating in time unison as a proposed output with a fixed constant delay for the logic function being simulated;and delaying said proposed output from a final output for a delay time specific to said logic function being simulated.
Claim 3
Dependent Claim
36 words
The method of claim 1, wherein said delay time is further specific to whether said proposed output has changed from a high to a low logic level or from a low to a high logic level.
Claim 4
Independent Claim
46 words
The method of either of claims 1 or 2, further comprising the steps of: detecting the presence of a glitch in said proposed output of a duration less than the corresponding delay time of said logic function being simulated;and inhibiting said glitch from said final output.
Claim 5
Dependent Claim
138 words
The method of claim 1 comprising the steps of: simulating one or more time sequential logic functions in each of a plurality of basic processors, said logic functions in each of said basic processors being simulated in successive work cycles of logic operations; determining, in each of said basic processors in each of said work cycles, a minimum work space value as a minimum time to a next successive logic operation among all logic functions simulated by said basic processor for each said work cycle; determining a global minimum work space value among all said basic processors for each said work cycle as a minimum one of work space values among all of said basic processors;and advancing each of said basic processors in time sequence in each of said work cycles by said global minimum work space value.
Claim 6
Dependent Claim
76 words
The method of claim 4, wherein said step of determining a minimum time to a next successive logic operation comprises: calculating a time to a predicted simulated logic function output transition time in accordance with a stored delay time for each logic function to be simulated during each said work cycle;and storing a minimum calculated time to a predicted simulated function output transition time among all of said logic functions simulated during each said work cycle.
Claim 7
Dependent Claim
109 words
The method of claim 5, wherein said step of calculating a time to a predicted simulated logic function output transition time comprises: for an initial work cycle and for a first work cycle following a transition in said simulated function output for the function simulated, subtracting said global minimum work space value from said stored delay time for each said simulated logic function and storing the difference;and repetitively for successive work cycles, for each said simulated logic function, and until a predicted transition occurs in said simulated logic function output, subtracting said minimum work space value from said difference and replacing said difference with a new difference thus calculated.
Claim 8
Dependent Claim
43 words
The method of claim 5, wherein said delay time is one of a first delay time value corresponding to low-to-high transitions and a second delay time value corresponding to high-to-low transitions of said simulated logic function output for each said simulated logic function.
Claim 9
Dependent Claim
58 words
The method of claim 7, further comprising the step of: selecting one of said first and second delay time values in accordance with a state of a simulated logic function output in a present work cycle and in a work cycle immediately prior to a present work cycle where a transition of a simulated logic function output occurs.
Claim 10
Independent Claim
41 words
The method of any of claims 4-8 further comprising the steps of: detecting presence of a glitch having a duration less than a corresponding delay time of a logic function being simulated;and inhibiting said glitch in a simulated logic function output.
Claim 11
Dependent Claim
129 words
A logic function simulator comprising a plurality of basic processors, a control processor, and an inter-processor switch interconnecting said basic processors and said control processor, each of said basic processors comprising: means for storing delay times for each logic function simulated by that basic processor; means for determining a time to a next successive logic operation for each said simulated logic function in accordance with a corresponding delay time; means for determining a minimum work space value as a minimum time to a next successive logic operation among all said simulated logic functions;and means for advancing said basic processor in time sequence by a global minimum work space value, said global minimum work space value being a minimum one of minimum work space values among all said basic processors.
Claim 12
Dependent Claim
129 words
A logic function simulator comprising a plurality of basic processors, a control processor, and an inter-processor switch interconnecting said basic processors and said control processor, each of said basic processors comprising: means for storing delay times for each logic function simulated by that basic processor; means for determining a time to a next successive logic operation for each said simulated logic function in accordance with a corresponding delay time; means for determining a minimum work space value as a minimum time to a next successive logic operation among all said simulated logic functions;and means for advancing said basic processor in time sequence by a global minimum work space value, said global minimum work space value being a minimum one of minimum work space values among all said basic processors.
Claim 13
Dependent Claim
46 words
The logic function simulator of claim 10, wherein said means for determining a time to a next successive logic operation for each said simulated logic function comprises means for subtracting said global minimum work space value from a delay time for each said simulated logic function.
Claim 14
Dependent Claim
49 words
The logic function simulator of any one of claims 10-11 further comprising: means for detecting the presence of a glitch in a simulated output for each said simulated logic function of a duration less than the corresponding delay time of said simulated logic function;and means for inhibiting said glitch.
Claim 15
Dependent Claim
106 words
The logic function simulator of claims 10-12, comprising means in each of said basic processors for storing delay times for each logic function being simulated, said delay times including delay times for each of a low-to-high and high-to-low transition of each simulated output of each simulated logic function;means for selecting one of said delay times corresponding to a low-to-high transition or a high-to-low transition in accordance with a type of transition predicted for each said simulated logic function;and means for accumulatively subtracting a global minimum work space value from the selected delayed time for each said simulated logic function, said global minimum work space value being.
References Cited (Backward Citations)
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