Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
325 words
An apparatus for dividing one element a i of a Galois field GF(2 m ) consisting of 2 m elements by another element aj, thus performing a division of a i - α j (= α i-j ), where a is the root of a modulus polynomial F (x) , said apparatus comprising: a plurality of first linear shift registers (A 1 ), (A 2 ), (A3), (A4), one of which receives data representing the element α j and the others of which receive the same data through a N l, aN2, α N3 , ... multiplier circuits (where 1 < Nl < N2, ...) (51), (52), (53), respectively; a plurality of second linear shift registers (B 1 ), (B 2 ), (B 3 ), (B 4 ), one of which receives data representing the element α i and the others of which receive the same data through a Nl , a N2, a N3, ... multiplier circuits (where 1 < N2 < N2, ...) (58), (59), (60), respectively; a plurality of "1" detector circuits (54), (55), (56), (57) connected to the outputs of said first linear shift registers, respectively; shift means for shifting said first linear shift registers (A 1 ), (A 2 ), (A3), (A4) and said second linear shift registers (B 1 ), (B 2 ), (B 3 ), (B 4 ) several times until any one of said "1" detector circuits (54), (55), (56), (57) detects "1"; a plurality of 2-input gate circuits (61), (62), (63), (64) connected at one input terminal to the outputs of said second linear shift registers, respectively, and at the other input terminal to the outputs of said "1" detector circuits, respectively; and output means (65) for delivering the output data from the second linear shift register corresponding to the first linear shift register coupled to the "1" detector circuit, said output data representing the quotient of the division of a i - α j .
Claim 2
Independent Claim
325 words
An apparatus for dividing one element a i of a Galois field GF(2 m ) consisting of 2 m elements by another element aj, thus performing a division of a i - α j (= α i-j ), where a is the root of a modulus polynomial F (x) , said apparatus comprising: a plurality of first linear shift registers (A 1 ), (A 2 ), (A3), (A4), one of which receives data representing the element α j and the others of which receive the same data through a N l, aN2, α N3 , ... multiplier circuits (where 1 < Nl < N2, ...) (51), (52), (53), respectively; a plurality of second linear shift registers (B 1 ), (B 2 ), (B 3 ), (B 4 ), one of which receives data representing the element α i and the others of which receive the same data through a Nl , a N2, a N3, ... multiplier circuits (where 1 < N2 < N2, ...) (58), (59), (60), respectively; a plurality of "1" detector circuits (54), (55), (56), (57) connected to the outputs of said first linear shift registers, respectively; shift means for shifting said first linear shift registers (A 1 ), (A 2 ), (A3), (A4) and said second linear shift registers (B 1 ), (B 2 ), (B 3 ), (B 4 ) several times until any one of said "1" detector circuits (54), (55), (56), (57) detects "1"; a plurality of 2-input gate circuits (61), (62), (63), (64) connected at one input terminal to the outputs of said second linear shift registers, respectively, and at the other input terminal to the outputs of said "1" detector circuits, respectively; and output means (65) for delivering the output data from the second linear shift register corresponding to the first linear shift register coupled to the "1" detector circuit, said output data representing the quotient of the division of a i - α j .
Claim 3
Dependent Claim
87 words
An apparatus according to claim 1, wherein said α N1 , α N2 , α N3 , ... multiplier circuits (51), (52), (53), (58), (59), (60) are α· ·2 m , α· ·2 m , α· ·2 m , ... multiplier circuits, and said first linear shift registers (A 1 ), (A 2 ), (A3), (A4) and said second linear shift registers (B 1 ), (B 2 ), (B 3 ), (B 4 ) multiply the data stored in them by a every time they are shifted.
Claim 4
Dependent Claim
87 words
An apparatus according to claim 1, wherein said α N1 , a N2 , a N3 , ... multiplier circuits (51), (52), (53), (58), (59), (60) are a l , a 2 , a3, ... multiplier circuits, and said first linear shift registers (A 1 ), (A 2 ), (A3), (A4) and said second linear shift registers (B l ), (B 2 ), (B 3 ), (B 4 ) multiply the data stored in them by α NO every time they are shifted, where NO > 2.
Claim 5
Dependent Claim
31 words
An apparatus according to claim 1, wherein said each of said "1" detector circuits (54), (55), (56), (57) comprises an inverter (I 10 ) and a NOR gate (NOR 11 ).
Claim 6
Dependent Claim
94 words
An apparatus according to claim 1, wherein said shift means comprises a NOR gate (NOR 10 ) for receiving the outputs from said "1" detector circuits (54), (55), (56), (57) and an AND gate (AND 11 ) for generating the product of the output from the NOR gate (NOR 10 ) and a clock pulse (Cp), the output from said AND gate (AND 11 ) being used to shift said first (A 1 ), (A 2 ), (A3), (A4) and second linear shift registers (B 1 ), (B2) , (B3) , (B 4 ).
Claim 7
Dependent Claim
29 words
An apparatus according to claim 1, wherein each of said 2-input gate circuits (61), (62), (63), (64) comprises a plurality of AND gates (AND 20 ) to (AND27) .
Claim 8
Dependent Claim
41 words
An apparatus according to claim 1, wherein said output means (65) comprises a plurality of OR gates (OR 20 ) to (OR 27 ) each for generating the logical sum of outputs from said 2-input gate circuits (61), (62), (63), (64).