Patent US2825160A successfully refreshed from Google Patents.
Patent EP0095721A2 successfully refreshed from Google Patents.
EP0095721A2
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1983-05-25
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Granted: —
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Expires: 2003-05-25
Abstract
Abstract A semiconductor memory device is comprised of: a semiconductor memory (21, 27) having a plurality of memory cells (22 11 , 22 12 , ... 28 11 , 28 12 , ...) arrayed in a matrix, a memory area of the memory including a main memory section (21) and an auxiliary memory section (27); a plurality of row lines (24 M1 , 24 M2 , ... 24 A1 , 24 A2 , ...) for selecting the memory cells connected to the memory cells; a plurality of power source lines (24 M1 , 24 M2 , ... 24 A1 , 24 A2 , ...) provided corresponding to the row lines; and a fuse element (FD M1 , FD M2 , ... FD A1 , FD A2 , ...) for separating or disconnecting from a power source the power source lines connected to the memory cells in an unused memory area of the semiconductor memory.
Inventors
- 👤 Hiroshi Iwahashi
- 👤 Kiyofumi Ochii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 21:36
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/83; G11C29/832
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
68 words
A semiconductor memory device comprising: a main semiconductor circuit (2); and an auxiliary semiconductor circuit (27) used in place of a defective portion of said main semiconductor circuit if the defective portion is present in said main semiconductor circuit; characterized by further comprising means (FD M1 , FD M21 ... FD A1 , FD A2 , ...) for disconnecting said defective circuit portion from said main semiconductor circuit.
Claim 2
Dependent Claim
68 words
A semiconductor memory device comprising: a main semiconductor circuit (2); and an auxiliary semiconductor circuit (27) used in place of a defective portion of said main semiconductor circuit if the defective portion is present in said main semiconductor circuit; characterized by further comprising means (FD M1 , FD M21 ... FD A1 , FD A2 , ...) for disconnecting said defective circuit portion from said main semiconductor circuit.
Claim 3
Dependent Claim
44 words
A semiconductor memory device according to claim 1, characterized by further comprising means (C M1 , C M2 , ... C A1 , C A2 , ...) for disconnecting said auxiliary semiconductor circuit from a power source when said auxiliary memory is not used.
Claim 4
Dependent Claim
189 words
A semiconductor memory device comprising: memory means with a plurality of memory cells (22 11 , 22 12 , ... 28 11 , 28 12 , ...) arrayed in a matrix and having a main memory area (21) and an auxiliary memory area (27) used in place of a part of said main memory area; a plurality of row lines (R M1 , R M2 , ... R A1 , R A2 , ...) connected to said memory cells for selectively specifying said memory cells; a plurality of column lines (Cl, C2, ...) connected to said memory cells, through which data is read out; and power source lines (24 M1 , 24 M2 , ..., 24 A1 , 24 A2 , ...) provided corresponding to said row lines and connected to said memory cells connected to said corresponding row lines; characterized by further comprising means (FD Ml , FD M2 , ... FD A1 , FD A2 , ...) for disconnecting from said power source said power source lines, which are connected to said memory cells in the unused memory area, of the plurality of said power source lines.
Claim 5
Dependent Claim
189 words
A semiconductor memory device comprising: memory means with a plurality of memory cells (22 11 , 22 12 , ... 28 11 , 28 12 , ...) arrayed in a matrix and having a main memory area (21) and an auxiliary memory area (27) used in place of a part of said main memory area; a plurality of row lines (R M1 , R M2 , ... R A1 , R A2 , ...) connected to said memory cells for selectively specifying said memory cells; a plurality of column lines (Cl, C2, ...) connected to said memory cells, through which data is read out; and power source lines (24 M1 , 24 M2 , ..., 24 A1 , 24 A2 , ...) provided corresponding to said row lines and connected to said memory cells connected to said corresponding row lines; characterized by further comprising means (FD Ml , FD M2 , ... FD A1 , FD A2 , ...) for disconnecting from said power source said power source lines, which are connected to said memory cells in the unused memory area, of the plurality of said power source lines.
Claim 6
Dependent Claim
22 words
A semiconductor memory device according to claim 3, characterized in that said unused memory area is present in said main memory area.
Claim 7
Dependent Claim
22 words
A semiconductor memory device according to claim 3, characterized in that said unused memory area is present in said auxiliary memory area.
Claim 8
Dependent Claim
28 words
A semiconductor memory device according to claim 3, characterized in that said power source lines are each commonly used for memory cells connected to two adjacent row lines.
Claim 9
Dependent Claim
91 words
A semiconductor memory device according to claim 3, characterized by further comprising a decoder circuit having a memory area (23) divided into a main decoder area for selecting a memory cell of said main memory area and an auxiliary decoder area (29) for selecting a memory cell in said auxiliary memory area, and means (C M1 , C M2 , ..., C Al , C A2 , ...) for disconnecting from said power source an area of said decoder circuit corresponding to a memory area not used of said memory means.
Claim 10
Dependent Claim
93 words
A semiconductor memory device according to claim 3, characterized by further comprising a decoder circuit having a memory area (23) divided into a main decoder area for selecting a memory cell of said main memory area and an auxiliary decoder area (29) for selecting a memory cell in said auxiliary memory area, and means (C Ml , C M2 , ..., C Al , C A2 , ...) for disconnecting from said power source a memory area not used of said memory means and a corresponding area not used of said decoder circuit.
Claim 11
Dependent Claim
77 words
A semiconductor memory device according to claim 3, characterized in that said column lines Cl to Cn are connected to a power source (VD), a sense amplifier (91) is connected between said column lines and said power source, and means (99, 100, 101, 102) for disconnecting from said power source either of said sense amplifier and said column lines, which are connected to said main memory area and an unused memory area of said auxiliary memory area.
Claim 12
Dependent Claim
32 words
A semiconductor memory device according to claim 3, characterized in that said disconnecting means includes means (21) for selectively connecting or disconnecting said power source lines to and from said power source.
Claim 13
Dependent Claim
51 words
ll. A semiconductor memory device according to claim 10, characterized in that said connecting or disconnecting means includes switching means (121) inserted in each of said power source lines, and means (131, 151) for selectively disconnecting said switching means from each of said power source lines by controlling said switching means.
Claim 14
Dependent Claim
19 words
A semiconductor memory device according to claim 11, characterized in that said switching means is an MOS transistor (121).
Claim 15
Dependent Claim
30 words
A semiconductor memory device according to claim 12, characterized in that said disconnecting means controls said MOS transistor according to a logic level of the signal of said row line.
Claim 16
Dependent Claim
18 words
A semiconductor memory device according to claim 1, characterized in that said defective portion is a memory cell.
References Cited (Backward Citations)
No citation records indexed.
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