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EP0094254A2
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EP
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Integrated scrambler-encoder using PN sequence generator
Assignee: Tandem Computers Inc
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Filing: 1983-05-11
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Granted: —
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Expires: 2003-05-11
Abstract
Abstract Simplified apparatus for performing integrated scrambling and encoding or descrambling and decoding of block code digital transmissions is disclosed. The system involves setting the scrambling length equal to an integer multiple of the block length, and then implementing a pseudorandom number sequence generator within the block length counter. The output of the pseudorandom number sequence generator is then logically combined with the incoming data to provide scrambled data, simplifying the complexity of the encoder or decoder significantly.
Inventors
- 👤 Edward J. Weldon, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 05:09
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03828; H04L25/03866
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
56 words
An encoder for a digital transmission system having input means for receiving data, characterised by counter means responsive to the input means and including a plurality of counting stages for counting block lengths, and exclusive OR means associated with at least one of the counting stages for causing the counter means to generate pseudorandom number sequences.
Claim 2
Dependent Claim
56 words
An encoder for a digital transmission system having input means for receiving data, characterised by counter means responsive to the input means and including a plurality of counting stages for counting block lengths, and exclusive OR means associated with at least one of the counting stages for causing the counter means to generate pseudorandom number sequences.
Claim 3
Dependent Claim
57 words
A scrambler-encoder for use in a digital transmission system characterised by input means for receiving incoming data, block code encoding means including a plurality of counter stages for counting code lengths, and scrambling means interconnected between at least one of the counter stages of the encoding means for causing the counter stages to generate pseudorandom number sequences.
Claim 4
Dependent Claim
57 words
A scrambler-encoder for use in a digital transmission system characterised by input means for receiving incoming data, block code encoding means including a plurality of counter stages for counting code lengths, and scrambling means interconnected between at least one of the counter stages of the encoding means for causing the counter stages to generate pseudorandom number sequences.
Claim 5
Dependent Claim
113 words
A scrambler-encoder.as claimed in claim 2 characterised by clock means for generating clock signals, the scrambling means being responsive to the clock means for providing count signals and the pseudorandom number sequences, logic combining means responsive to the incoming data on the input means and the pseudorandom number sequence generator means for providing scrambled data, parity check generator means responsive to the scrambled data and the clock means for generating parity bits, and switching logic means including ouput means and responsive to the sequence generator means and the clock means for determining during which periods the output means will receive scrambled data and during which periods the ouput means will receive parity bits.
Claim 6
Dependent Claim
16 words
A scrambler-encoder substantially as herein described with reference to and as illustrated in the accompanying drawings.
Claim 7
Dependent Claim
16 words
A scrambler-encoder substantially as herein described with reference to and as illustrated in the accompanying drawings.
References Cited (Backward Citations)
No citation records indexed.
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