Abstract An apparatus for controlling the writing of data from a processor (1) into a memory (4) having different read and write times, wherein the memory (4) is connected directly to the processor (1) through address (7) and data (8) buses without the use of an input/output port. A timer circuit (5) is connected to the buses (7, 8) and memory (4) and is controlled by the processor (1) to produce a write timing signal which controls the writing of data into the memory (4). The processor (1) is placed in a holding state based on the write timing signal for a period long enough to assure that the data will be written into the memory (4) in its entirety.
An apparatus for controlling the writing of data from a processor into a memory having different read and write times, wherein said memory is connected directly to the processor through address and data buses, comprising: a timer circuit connected to the memory and to the buses and responsive to a command from the processor for generating a write timing signal applied to the memory, said write timing signal having a duration commensurate with the write time of the memory so that data from the processor is written into the memory via the data bus within said write time, and a stand-by control circuit connected to the processor and to said timer circuit and responsive to an enable signal from said timer circuit for holding the processor in the current write processing cycle long enough for the data from the processor to be written into the memory.
Claim 2
Independent Claim
146 words
An apparatus for controlling the writing of data from a processor into a memory having different read and write times, wherein said memory is connected directly to the processor through address and data buses, comprising: a timer circuit connected to the memory and to the buses and responsive to a command from the processor for generating a write timing signal applied to the memory, said write timing signal having a duration commensurate with the write time of the memory so that data from the processor is written into the memory via the data bus within said write time, and a stand-by control circuit connected to the processor and to said timer circuit and responsive to an enable signal from said timer circuit for holding the processor in the current write processing cycle long enough for the data from the processor to be written into the memory.
Claim 3
Dependent Claim
46 words
The apparatus according to claim 1, wherein said timer circuit supplies said stand-by control circuit with a disable signal when the writing of the data into the memory is completed, said stand-by control circuit responding by freeing the processor for execution of a subsequent processing cycle.
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