Patent EP0091819A2 successfully refreshed from Google Patents.
EP0091819A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Charge-coupled device with data reference-level circuit
Assignee: Sony Corp
•
Filing: 1983-04-12
•
Granted: —
•
Expires: 2003-04-12
Abstract
Abstract A digital memory comprises a charge coupled device (CCD) that includes a reference signal storage section. The digital input to the CCD includes an input reference signal and an information signal having a plurality of data levels, for example, a digital "0" and "1". The input reference signal includes a reference bit at the higher data level. The reference signal storage section divides the level of the reference bit to provide a reference level signal halfway between the two data levels. Thus, any shift in the data levels due, for example, to temperature changes in the CCD, affects the reference level signal to the same degree and the reference level can be kept exactly halfway between the data levels.
Inventors
- 👤 Tadakuni Narabu
- 👤 Maki Sato
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 09:53
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; G11C19/282; G11C19/285; G11C27/00; G11C27/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
138 words
A digital memory comprising a charge transfer device including information storage means for storing digital information having a plurality of data levels and providing said digital information to a sensing means after storing it for a predetermined time and reference signal means for supplying a reference level signal having a level between the data levels for use by the sensing means to distinguish between the data levels; characterized in that said reference signal means comprises reference signal storage means (28) for accepting an input reference signal and providing said reference level signal (S REF ) at a predetermined time after accepting said input reference signal, said reference signal storage means being maintained at operating conditions relative to the information storage means so that said level of said reference level signal relative to said data levels remains substantially constant.
Claim 2
Dependent Claim
138 words
A digital memory comprising a charge transfer device including information storage means for storing digital information having a plurality of data levels and providing said digital information to a sensing means after storing it for a predetermined time and reference signal means for supplying a reference level signal having a level between the data levels for use by the sensing means to distinguish between the data levels; characterized in that said reference signal means comprises reference signal storage means (28) for accepting an input reference signal and providing said reference level signal (S REF ) at a predetermined time after accepting said input reference signal, said reference signal storage means being maintained at operating conditions relative to the information storage means so that said level of said reference level signal relative to said data levels remains substantially constant.
Claim 3
Dependent Claim
69 words
A digital memory as in claim 1; wherein said information storage means comprises a charge transfer device (12; 112; 212; 12B; 12B') and said reference signal storage means comprises a charge transfer device (12; 112; 212; 12A; 12A') maintained at operating conditions relative to said information storage means so that said reference level signal (S REF ) is maintained at a level halfway between two of said data levels.
Claim 4
Dependent Claim
27 words
A digital memory as in claim 2; wherein said information storage means and said reference signal storage means comprise the same charge coupled device (12; 112; 212).
Claim 5
Dependent Claim
109 words
A digital memory as in claim 1; wherein said reference signal storage means (28) comprises a charge coupled device (12;112;212;12A;12A') maintained at the same operating temperature as the information storage means and having a plurality of channels (201, 202; 211, 2121, 2122; 221, 222; 701, 702) for transferring said input reference signal, said input reference signal has a level substantially the same as a higher one of said data levels and said channels include at least one divider channel (202; 2121, 2122; 222; 702) for dividing said input reference signal to provide said reference level signal (S REF ) at a. level halfway between two of said data levels.
Claim 6
Dependent Claim
57 words
A digital memory as in claim 4; wherein said charge coupled device includes said information storage means (27), an input register (21) for accepting a block of data comprising said input reference signal and said information and an output register (23) for providing a block of data comprising said reference level signal and said information (FIG. 4).
Claim 7
Dependent Claim
61 words
A digital memory as in claim 4 or 5; wherein said input reference signal is at a level the same as the higher level of two data levels and said divider channel comprises an output channel (202A, 202B; 2121A, 2121B, 2122A, 2122B; 2221A, 2221B, 2222; 702A, 702B) for providing said reference level signal at a level halfway between said data levels.
Claim 8
Dependent Claim
113 words
A digital memory as in claim 4 or 5; wherein said divider channel comprises a first divider channel (2121) for accepting a first input reference signal at a level the same as the middle level of three equally spaced data levels and a pair of first divider output channels (2121A, 2121B) for providing first reference level signals at a level between the lowest and the middle data levels and a second divider channel (2122) for accepting a second input reference signal at a level the same as the highest level of said data levels and second divider output channel (2122A, 2122B) for providing a second reference level signal at the middle data level.
Claim 9
Dependent Claim
96 words
A digital memory as in claim 4 or 5; wherein said divider channel comprises a first divider channel (222) for accepting an input reference signal at a level the same as the highest level of three equally spaced data levels, a pair of intermediate output channels (2221, 2222) for providing a pair of first reference level signals at the middle data level and a pair of final divider channels (2221A, 2221B) for dividing one of said first reference level signals into a pair of second reference level signals between the lowest and the middle data levels.
Claim 10
Dependent Claim
26 words
A digital memory as in any of claims 4 to 8; wherein said reference signal storage means includes a buffer channel for storing a buffer signal.
Claim 11
Dependent Claim
70 words
A digital memory as in any of claims 6 to 9; wherein said information storage means comprises an information input register (61), an information charged coupled device (62) and an information output register (63) and said reference signal storage means comprises a reference input register (71) for accepting an input reference signal from a reference signal generator (40), a reference charge coupled device (72) and a reference output register (73).
Claim 12
Dependent Claim
38 words
A digital memory as in any of claims 5 to 9; wherein said output register provides said block of data to a sample and hold circuit (13) for providing said reference level signal to the sense amplifier (14).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.