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EP0091200A2
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EP
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Clock recovery apparatus
Assignee: Laser Magnetic Storage International Inc
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Filing: 1983-03-04
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Granted: —
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Expires: 2003-03-04
Abstract
Abstract A clock recovery apparatus for generating an output clock signal locked to the phase and frequency of an input data rate which comprises a sequence of encoded data signals, comprises a data detector (10) for detecting the data signals, an oscillator (14), for generating a first clock signal having a frequency of oscillation representative of the value of an analog signal, and a phase detector (16) comprising a memory (56) and a register (58). The register is responsive to the first clock signal to generate the output clock signal and the memory is responsive to the count of the register and the data detector to determine the relative phase relationship between each data signal and the output clock signal and to store information pertaining to the relative phase relationship. A counter (30) contains a count and a converter (34) is responsive to the count to generate the analog signal. The memory is responsive to the relative phase relationship of a data signal and to the stored information pertaining to a previous relative phase relationship to operate the counter to increment or decrement selectively the count therein to alter the frequency of the first clock signal.
Inventors
- 👤 Richard Charles Carickhoff
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 17:31
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
236 words
A clock recovery apparatus for generating an output clock signal locked to the phase and frequency of an input data rate, said input data rate comprising a sequence of encoded data signals, said apparatus characterised by comprising: data detector means (10) for detecting said data signals; oscillator means (14) responsive to an analog signal for generating a first clock signal having a frequency of oscillation representative of the value of said analog signal; phase detector means (16) comprising memory means (56) and register means (58), said register means (58) being responsive to said first clock signal for cyclicly counting the pulses of said first clock signal to generate said output clock signal, and said memory means (56) being responsive to the count in said register means (58) and to said data detector means (10) for determining the relative phase relationship between each data signal and said output clock signal and for storing information pertaining to said relative phase relationship; and counter means (30) for containing a count; converter means (34) responsive to the count in said counter means (30) for generating said analog signal, said memory means, in operation, being responsive to the relative phase relationship of a data signal and to the stored information pertaining to a previous relative phase relationship to operate said counter means (30) to increment or decrement selectively the count therein thereby to alter the frequency of said first clock signal.
Claim 2
Dependent Claim
236 words
A clock recovery apparatus for generating an output clock signal locked to the phase and frequency of an input data rate, said input data rate comprising a sequence of encoded data signals, said apparatus characterised by comprising: data detector means (10) for detecting said data signals; oscillator means (14) responsive to an analog signal for generating a first clock signal having a frequency of oscillation representative of the value of said analog signal; phase detector means (16) comprising memory means (56) and register means (58), said register means (58) being responsive to said first clock signal for cyclicly counting the pulses of said first clock signal to generate said output clock signal, and said memory means (56) being responsive to the count in said register means (58) and to said data detector means (10) for determining the relative phase relationship between each data signal and said output clock signal and for storing information pertaining to said relative phase relationship; and counter means (30) for containing a count; converter means (34) responsive to the count in said counter means (30) for generating said analog signal, said memory means, in operation, being responsive to the relative phase relationship of a data signal and to the stored information pertaining to a previous relative phase relationship to operate said counter means (30) to increment or decrement selectively the count therein thereby to alter the frequency of said first clock signal.
Claim 3
Dependent Claim
47 words
Apparatus as claimed in claim 1 characterised in that said memory means (56) is responsive to a relative phase relationship exceeding a predetermined amount to operate said counter means to increment or decrement selectively the count therein to thereby alter the frequency of said first clock signal.
Claim 4
Dependent Claim
50 words
Apparatus as claimed in claim 1 or 2 characterised in that said memory means (56) is responsive to a relative phase relationship exceeding a predetermined amount to operate said register means (58) to selectively advance or retard the count therein to thereby alter the phase of said output clock signal.
Claim 5
Dependent Claim
91 words
Apparatus as claimed in claim 3 characterised in that said register means (58) is a sixteen count register providing one full output clock cycle for each sixteen first clock cycles, said memory means (56) being operable to increment or decrement selectively the count in said register means (58) by one count if the memory means (56) detects a phase relationship greater than 6.25% and to increment or decrement selectively the count in said register means (58) by two counts if the memory means (56) detects a phase relationship greater than 31.25%.
Claim 6
Dependent Claim
91 words
Apparatus as claimed in claim 4 characterised in that said memory means (56) sets a flag signal whenever it detects a relative phase relationship greater than 18.75% and resets the flag signal whenever it detects a relative phase relationship less than 18.75% in a direction opposite that of the stored information pertaining to a previous relative phase relationship, the count in said register means (58) being selectively advanced or retarded when said memory means (56) detects a phase relationship between 6.25% and 18.75% only if said flag signal is not set.
Claim 7
Dependent Claim
209 words
A clock recovery apparatus for generating an output clock signal locked to the phase and frequency of an input data rate, said input data rate comprising a sequence of encoded data signals, said apparatus comprising: data detector means (10) for detecting said data signals; oscillator means (14) responsive to an analog signal for generating a first clock signal having a frequency of oscillation representative of the value of said analog signal; phase detector means (16) comprising memory means (56) and register means (58), said register means (58) being responsive to said first clock signal for cyclicly counting the oscillations of said first clock signal to generate said output clock signal, and said memory means (56) being responsive to the count in said register means (58) and to said data detector means (10) for determining the relative phase relationship between each data signal and said output clock signal; counter means (30) for containing a count; and converter means (34) responsive to the count in said counter means for generating said analog signal, said memory means being responsive to a relative phase relationship exceeding a predetermined amount to operate said counter means (30) to increment or decrement selectively the count therein thereby to alter the phase of said first clock signal.
Claim 8
Dependent Claim
209 words
A clock recovery apparatus for generating an output clock signal locked to the phase and frequency of an input data rate, said input data rate comprising a sequence of encoded data signals, said apparatus comprising: data detector means (10) for detecting said data signals; oscillator means (14) responsive to an analog signal for generating a first clock signal having a frequency of oscillation representative of the value of said analog signal; phase detector means (16) comprising memory means (56) and register means (58), said register means (58) being responsive to said first clock signal for cyclicly counting the oscillations of said first clock signal to generate said output clock signal, and said memory means (56) being responsive to the count in said register means (58) and to said data detector means (10) for determining the relative phase relationship between each data signal and said output clock signal; counter means (30) for containing a count; and converter means (34) responsive to the count in said counter means for generating said analog signal, said memory means being responsive to a relative phase relationship exceeding a predetermined amount to operate said counter means (30) to increment or decrement selectively the count therein thereby to alter the phase of said first clock signal.
Claim 9
Dependent Claim
53 words
Apparatus according to any preceding claim characterised by including second converter means (36) responsive to said phase detector means (16) for generating a second analog signal representative of a phase shift to be accomplished, means (40) for adding said first-named analog signal and said second analog signal to operate said oscillator means (14).
References Cited (Backward Citations)
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