Power MOSFET

Claim 1

A power MOSFET having a semiconductor substrate used as a common drain region, a base region for dividing a surface of said semiconductor substrate into a plurality of small regions, and a plurality of source regions opposing said drain region through said base region, characterized in that said power MOSFET comprises: a plurality of projections (22a-1, 22a-2) formed integrally on the surface of said semiconductor substrate (21) of one conductivity type which serves as said drain region, each of said plurality of projections having a rectangular surface, and said plurality of projections having a plurality of rows of projections and a plurality of columns of projections which are respectively spaced apart from each other by predetermined distances such that said projections (22a-l, 22a-2) of one of said plurality of rows of projections are offset by a distance corresponding to half of a long side of said rectangular surface with respect to said projections (22b-l, 22b-2) of an adjacent one of said plurality of rows of projections; a base region (23) of another conductivity type formed to cover a surface portion of said semiconductor substrate (21) which excludes surfaces of said plurality of projections (22a-l, 22a-2); a source region (24) of said one conductivity type which is formed to surround said plurality of projections (22a-1, 22a-2) so as to sandwich said base region (23a, 23b) having a predetermined width therebetween; an insulating film (32) formed to cover surfaces of said plurality of projections (22a-1, 22a-2), said base region (23), and said source region (24); a plurality of gate films (33a - 33e) formed on at least said surfaces of said plurality of projections (22a-1, 22a-2) and said base region (23a, 23b) and which are formed on said insulating film (32); a plurality of source electrode contacts (25a) formed such that each of said source electrode contacts is formed between first and second projections (22a-l, 22a-2) of said plurality of projections which are longitudinally adjacent to each other so as to connect said source region (24) respectively formed around said first projection (22a-l) and said second projection (22a-2); and a plurality of gate electrode contacts (33c-1, 33d-l, 33e-l) which respectively extend through said insulating film (32) to be connected to said plurality of gate films (33a - 33e).