Patent EP0090963A2 successfully refreshed from Google Patents.
EP0090963A2
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EP
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Method for making polycrystalline silicon film resistors
Assignee: International Business Machines Corp
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Filing: 1983-03-15
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Granted: —
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Expires: 2003-03-15
Abstract
Abstract A method for making polycrystalline silicon film resistors is described which includes deposition of a polycrystalline silicon layer (14, 34) of very fine grain size upon an insulator surface (12, 28), followed by ion implantation of boron equal to or slightly in excess of the solubility limit of the polycrystalline silicon. This ion implantation is normally done using a screen silicon dioxide surface layer. The structure may be annealed at temperatures of between 800°C to 1100°C for 15 to 180 minutes to control the grain size of the polycrystalline silicon layer, homogenize the distribution of the boron ions throughout the entire film thickness and to raise the concentration of the boron in the silicon grains to the solid solubility limit. The suitable electrical contacts (52, 54) are now made to the polycrystalline silicon layer to form the resistor.
Inventors
- 👤 Reinhard Glang
- 👤 San-Mei Ku
- 👤 Alfred Schmitt
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 09:31
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/30; H10P32/302
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
78 words
Method for making a polycrystalline silicon film resistor comprising: depositing a polycrystalline silicon layer (14, 34) of very fine grain.size upon an insulator surface (12, 28); ion implanting boron into said polycrystalline silicon layer approximately equal to or in excess of the solid solubility limit of said polycrystalline silicon; annealing said polycrystalline silicon layer to control the grain size of the said polycrystalline silicon layer resistor; and making contacts (18; 52, 54) to said layer as said resistor.
Claim 2
Dependent Claim
78 words
Method for making a polycrystalline silicon film resistor comprising: depositing a polycrystalline silicon layer (14, 34) of very fine grain.size upon an insulator surface (12, 28); ion implanting boron into said polycrystalline silicon layer approximately equal to or in excess of the solid solubility limit of said polycrystalline silicon; annealing said polycrystalline silicon layer to control the grain size of the said polycrystalline silicon layer resistor; and making contacts (18; 52, 54) to said layer as said resistor.
Claim 3
Dependent Claim
21 words
Method of claim 1 wherein said polycrystalline silicon is deposited by pyrolysis of silane at a temperature between 600 to 750°C.
Claim 4
Dependent Claim
15 words
Method of claim 1 wherein said insulator surface (12, 28) is composed of silicon dioxide.
Claim 5
Dependent Claim
21 words
Method of claim 3 wherein said silicon dioxide (28) forms a part of the dielectric isolation of an integrated circuit structure.
Claim 6
Dependent Claim
21 words
Method of claim 4 wherein said polycrystalline silicon layer (34) is formed simultaneously with an extrinsic polycrystalline silicon contact layer base.
Claim 7
Dependent Claim
44 words
Method of claim 1 wherein said ion implantation is accomplished to the extent that the boron concentration in polycrystalline silicon layer (14, 34) is between 3 x 10 19 ato ms/ c m 3 to 3 x 10 20 a t oms/cm 3 .
Claim 8
Dependent Claim
21 words
Method of claim 5 wherein said ion implantation is simultaneously done into said extrinsic base and said polycrystalline silicon resistor layer.
Claim 9
Dependent Claim
29 words
Method of claim 1 wherein said annealing is done at a temperature between 800 to 1100°C for 15 to 180 minutes to obtain grain sizes less than 150 nanometers.
Claim 10
Dependent Claim
66 words
Method of claim 8 wherein said annealing is done at a temperature between 800 to 1100°C for 15 to 180 minutes to simultaneously drive in the said boron from the external base contact into the monocrystalline silicon extrinsic base and to homogenize the distribution of said boron atoms and raise the concentration of said boron in the silicon grains to the solubility limit of said resistor.
Claim 11
Dependent Claim
23 words
Method of claim 1 and further comprising etching polycrystalline silicon layer (14, 34) to thin said layer prior to said ion implanting boron.
Claim 12
Dependent Claim
30 words
Method of claim 10 wherein said etching is by reactive ion etching or by wet pyrocatechol etching and said layer is thinned to a layer of less than 50 nanometers.
Claim 13
Dependent Claim
171 words
Method of forming an integrated circuit which includes an NPN transistor and a resistor comprising: providing a silicon semiconductor body having regions of monocrystalline silicon dielectrically isolated from one another by dielectric isolating regions (28, 30); providing a mask (32) over the surface of said body having said isolating regions therein covering all regions except those regions designated to be the extrinsic base regions (38); depositing a polycrystalline silicon layer (34) of very fine grain size over said mask and said designated extrinsic base regions; ion implanting boron equal to or in excess of the solid solubility limit of said polycrystalline silicon; annealing said polycrystalline silicon layer (34) to simultaneously control the grain size in said layer and drive in the said boron from the said layer into said designated external base region; removing portions of said polycrystalline silicon layer by lithography and etching to delineate external base contact and resistors in said polycrystalline silicon layer; and making contacts (50, 52, 54) to said external base contacts and to said resistors.
Claim 14
Dependent Claim
171 words
Method of forming an integrated circuit which includes an NPN transistor and a resistor comprising: providing a silicon semiconductor body having regions of monocrystalline silicon dielectrically isolated from one another by dielectric isolating regions (28, 30); providing a mask (32) over the surface of said body having said isolating regions therein covering all regions except those regions designated to be the extrinsic base regions (38); depositing a polycrystalline silicon layer (34) of very fine grain size over said mask and said designated extrinsic base regions; ion implanting boron equal to or in excess of the solid solubility limit of said polycrystalline silicon; annealing said polycrystalline silicon layer (34) to simultaneously control the grain size in said layer and drive in the said boron from the said layer into said designated external base region; removing portions of said polycrystalline silicon layer by lithography and etching to delineate external base contact and resistors in said polycrystalline silicon layer; and making contacts (50, 52, 54) to said external base contacts and to said resistors.
Claim 15
Dependent Claim
15 words
Method of claim 12 wherein said resistors are located over said dielectric isolating regions (28).
Claim 16
Dependent Claim
27 words
Method of claim 12 wherein said polycrystalline silicon layer (34) is partially thermally oxidized before said ion implanting boron to act as a screen silicon dioxide layer.
Claim 17
Dependent Claim
35 words
Method of claims 12 and 14 wherein the thickness of said polycrystalline silicon layer is between 30 to 500 nanometers and the thickness of said screen silicon dioxide layer is between 20 to 100 nanometers.
References Cited (Backward Citations)
No citation records indexed.
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