Memory system

Claim 2

A memory system comprising a main memory (13), a cache memory (11;36,32) and means (15) for writing a block of consecutive words into said main memory (13) by direct memory access, characterised by means (40,41,42,34) responsive to said means (15) for writing for simultaneously invalidating all of said words in said cache memory (11).

Claim 3

A memory system as claimed in claim 1, in which the means (40,41,42,34) for invalidating comprises means (40,41) for detecting the occurrence of said writing, and means (42) responsive to said means (40,41) for detecting for simultaneously invalidating all of said words in said cache memory (11;36,32).

Claim 4

A memory system as claimed in claim 2, in which said cache memory (11;36,32) includes means (36) for storing a validity bit for each word in said block, and said means (40,41,42,34) for invalidating includes means (42) for setting said validity bits to a predetermined state.

Claim 5

A memory system as claimed in claim 3, in which said means (40,41,42,34) for invalidating further includes means (34) for detecting the presence in said cache memory (11;36,32) of any word in said block.

Claim 6

A memory system as claimed in claim 3 or claim 4, in which said means (40,41) for detecting the occurrence of said writing further includes means (41) for detecting the writing of a predetermined word of said block.

Claim 7

A memory system as claimed in claim 5, in which said means (40,41) for detecting the writing of a predetermined word of said block comprises means (41) for detecting all zeros in low order bits of the address of said word.

Claim 8

A memory system (11) comprising an address register (30) for storing the physical address of a mer.iory location to be written, a memory (32,36) for storing the contents of said memory location and for storing the address bits for words stored in said memory, and means (34) for matching address bits of said address register (30) with address bits of said memory (32,36) in order to determine the presence within said memory of any word in said memory location, characterised in that the memory means (32,36) comprises a contents memory (32) for storing the contents of said memory location, addressed by low order word address bits of said address register (30) and a control memory (36) for storing high order tag address bits for a block of n words stored in said contents memory (32) and n validity bits, each said validity bit being associated with a distinct one of said n words stored in said contents memory (32), said control memory (36) being addressed by a first number of said low order word address bits of said address register (30), and further characterised by means (38,39) responsive to said matching means (34) for decoding a second number of said low order word address bits of said address register (30) and for matching said decoded number with n validity bits obtained from said control memory (36) in order to determine the presence within said contents memory of a corresponding one of said words, and means (42) responsive to said matching means (34) for simultaneously setting the n validity bits of the block of said memory location to a predetermined state within said control memory (36) when a word in the block of said memory location is present within said contents memory (32).

Claim 9

A memory system (11) comprising an address register (30) for storing the physical address of a mer.iory location to be written, a memory (32,36) for storing the contents of said memory location and for storing the address bits for words stored in said memory, and means (34) for matching address bits of said address register (30) with address bits of said memory (32,36) in order to determine the presence within said memory of any word in said memory location, characterised in that the memory means (32,36) comprises a contents memory (32) for storing the contents of said memory location, addressed by low order word address bits of said address register (30) and a control memory (36) for storing high order tag address bits for a block of n words stored in said contents memory (32) and n validity bits, each said validity bit being associated with a distinct one of said n words stored in said contents memory (32), said control memory (36) being addressed by a first number of said low order word address bits of said address register (30), and further characterised by means (38,39) responsive to said matching means (34) for decoding a second number of said low order word address bits of said address register (30) and for matching said decoded number with n validity bits obtained from said control memory (36) in order to determine the presence within said contents memory of a corresponding one of said words, and means (42) responsive to said matching means (34) for simultaneously setting the n validity bits of the block of said memory location to a predetermined state within said control memory (36) when a word in the block of said memory location is present within said contents memory (32).

Claim 10

A memory system as claimed in claim 7, in which said means (42) for setting said n validity bits to a predetermined state is further responsive to a number of low order bits of the address of said memory location.

Claim 11

A memory system as claimed in claim 7, further comprising a plurality of contents memories (32,33) and a plurality of control memories (42,43) in a set associative arrangement.