Patent EP0090566A2 successfully refreshed from Google Patents.
EP0090566A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor device package
Assignee: Fujitsu Ltd
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Filing: 1983-03-18
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Granted: —
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Expires: 2003-03-18
Abstract
Abstract A semiconductor device having a hermetically sealed package comprises a package substrate (1) having a gold layer (2), an integrated-circuit chip (5) attached to the gold layer, a metal terminal chip (6) attached to the gold layer to ground it. Bonding wires (10,12) connect the integrated-circuit chip (5) and the metal terminal chip (6) to leads (4). The package is completed by a cap (13), and glass layers (3,14) which seal it. The metal terminal chip (6) has a lower coating layer (9) made of a gold-silicon type of alloy for bonding to the gold layer (2) and an upper layer (8) of aluminium-silicon alloy to enable the bonding wires (10,12) to be bonded onto it. The bond strength of such a metal terminal chip (6) does not decrease when it is subject to a heat treatment when the package is sealed.
Inventors
- 👤 Susumu Kida
- 👤 Hayato Usami
- 👤 Hideji Aoki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 12:21
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/66; H10W72/00; H10W72/30; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H10W95/00; H10W70/67; H10W70/68; H10W70/682; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/5449; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/90; H10W72/931; H10W72/932; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/751; H10W90/754; H10W90/756; Y; Y10; Y10S; Y10S228/00; Y10S228/904; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
122 words
A semiconductor device comprising a package substrate (1) including a gold layer (2) and terminal areas, an integrated-circuit chip (5) attached to the gold layer (2), a metal terminal chip (6) attached to the gold layer (2), and bonding wires (10, 12) for electrically connecting the terminal areas to the integrated-circuit chip (5) and to the metal terminal chip (6) , the metal terminal chip (6) having an upper coating layer (8) of an aluminium or an aluminium-silicon alloy to enable the bonding wires (10, 12) to be bonded onto it, characterised in that the metal terminal chip (6) has a lower coating layer (9) of a gold-silicon type of alloy to enable it to be bonded onto the gold layer (2).
Claim 2
Dependent Claim
122 words
A semiconductor device comprising a package substrate (1) including a gold layer (2) and terminal areas, an integrated-circuit chip (5) attached to the gold layer (2), a metal terminal chip (6) attached to the gold layer (2), and bonding wires (10, 12) for electrically connecting the terminal areas to the integrated-circuit chip (5) and to the metal terminal chip (6) , the metal terminal chip (6) having an upper coating layer (8) of an aluminium or an aluminium-silicon alloy to enable the bonding wires (10, 12) to be bonded onto it, characterised in that the metal terminal chip (6) has a lower coating layer (9) of a gold-silicon type of alloy to enable it to be bonded onto the gold layer (2).
Claim 3
Dependent Claim
24 words
A semiconductor device according to claim 1, in which the metal chip (6) is made of an iron-nickel- cobalt alloy, or an iron-nickel alloy.
Claim 4
Dependent Claim
32 words
A semiconductor device according to claim 1 or claim 2, in which the gold-silicon type of alloy is an alloy of gold and silicon, or an alloy of gold, germanium and silicon.
Claim 5
Dependent Claim
74 words
A semiconductor device according to any one of the preceding claims, in which the package includes a cap (13) and glass layers (3, 14) on the substrate (1) and cap (13), the lower coating layer (9) on the metal terminal chip (6) maintaining its bond strength with the gold layer (2) when the package is heated to join and hermetically seal the cap (13) and the package (1) with the glass layers (3, 14).
Claim 6
Dependent Claim
38 words
A semiconductor device according to any one of the preceding claims, in which the gold-silicon type of alloy is an alloy of gold and silicon having a silicon content in a range from 1% to 8% by weight.
Claim 7
Dependent Claim
53 words
A semiconductor device according to any one of the claims 1 to 3, in which the gold-silicon type alloy is an alloy of gold, germanium and silicon having a silicon content in a range from 0.3% to 3% by weight and a germanium content in a range from 12 to 0% by weight.
References Cited (Backward Citations)
No citation records indexed.
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