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EP0090175A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Memory system

Assignee: International Business Machines Corp
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Filing: 1983-02-23
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Granted: —
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Expires: 2003-02-23
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Abstract

Abstract A single error correcting memory is constructed from partially good components on the design assumption that the components are all good. Those small number of logical lines containing double-bit errors are replaced, when detected, by good lines selected from a replacement area of the memory. The replacement area is provided by a flexibly dynamically deallocated portion of the main memory so that it can be selected from any section of the original memory by inserting the appropriate page address in the replacement page register. With such a memory architecture, until the first double-bit error is detected (either in testing or actual use), all pages may be used for normal data storage. When such an error is detected, some temporarily unused page in the memory is deallocated, that is rendered unavailable for normal storage, and dedicated to providing substitute lines. The same procedure is followed for subsequent faults. If the replacement area itself becomes defective, a different page may be chosen to provide substitute lines simply be providing a different address in the replacement page register.

Inventors

  • 👤 Russell William Lavallee
  • 👤 Meade Philip Ryan
  • 👤 Vincent Francis Sollitto, Jr.

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-01 23:01
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 96 words
A method of accessing a memory in logical lines, some of which may contain uncorrectable errors, comprising the steps of: fetching a logical line from said memory and determining whether it contains an uncorrectable error; if an uncorrectable error is determined, deallocating an undedicated portion of said memory; and comparing line addresses on future accesses to said memory to determine whether the logical line accessed is the line known to contain said uncorrectable error and, if comparison shows equality, dynamically substituting the line address of said undedicated portion for the address of line to be accessed.
Claim 2
Independent Claim 96 words
A method of accessing a memory in logical lines, some of which may contain uncorrectable errors, comprising the steps of: fetching a logical line from said memory and determining whether it contains an uncorrectable error; if an uncorrectable error is determined, deallocating an undedicated portion of said memory; and comparing line addresses on future accesses to said memory to determine whether the logical line accessed is the line known to contain said uncorrectable error and, if comparison shows equality, dynamically substituting the line address of said undedicated portion for the address of line to be accessed.
Claim 3
Dependent Claim 67 words
A memory system accessible in logical lines comprising a memory and means for determing the presence of an uncorrectable error in a logical line accessed in said memory, characterized by means for deallocating an undedicated portion of said memory and directing all future access from said logical line to said,undedicated portion of said memory, and means for storing corrected data in said undedicated portion of said memory.
Claim 4
Dependent Claim 67 words
A memory system accessible in logical lines comprising a memory and means for determing the presence of an uncorrectable error in a logical line accessed in said memory, characterized by means for deallocating an undedicated portion of said memory and directing all future access from said logical line to said,undedicated portion of said memory, and means for storing corrected data in said undedicated portion of said memory.
Claim 5
Dependent Claim 37 words
The memory system of claim 2, for reading or writing data, wherein the undedicated portion of said memory contains at least one logical line which is substituted for the error-containing logical line whenever the latter is addressed.
Claim 6
Dependent Claim 41 words
The memory system of claim 3, said memory system comprising at least one basic storage module (BSM), a memory controller controlling the transfer of data between the basic storage module and the remainder of the system and a maintenance console (Fig.1).
Claim 7
Dependent Claim 20 words
The memory system of claim 4, wherein said maintenance console includes means for determining the presence of an uncorrectable error.
Claim 8
Dependent Claim 26 words
The memory system of claim 4, wherein said memory controller includes an address replacement array (4) containing addresses,of said logical line and said error-containing logical line.

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