Dual polarity switchable operational amplifier circuit

Claim 2

A dual polarity switchable operational amplifier circuit having an input (5) and an output (6), said input being connected to two sets of amplifier inputs (2 and 3), means responsive to a polarity select signal for selecting one or other sets of amplifier inputs (2 or 3), the circuit being operable in response to a current input (5) to provide a corresponding voltage at its output (6), the voltage being of one polarity when one set of amplifier inputs (2) is selected and of the other polarity when the other set of amplifier inputs (3) is selected, characterised in that the gain of the amplifier operating in each polarity is determined by a feedback resistor (R1 or R2) associated with that polarity, the construction and arrangement being such that the portion of the amplifier associated with the non-selected set of amplifier inputs (2 or 3) is inactive, and has a high input impedance, so that it has substantially no effect on the operation of the portion of the amplifier associated with the selected set of amplifier inputs (3 or 2).

Claim 3

A circuit as claimed in claim 1, in which the amplifier comprises a first and second transistor long-tailed pair configuration (T1, T2) and a third and fourth transistor long-tailed pair configuration (T3, T4) connected to a bistable switch (T5, T6) operable in one state to cause only the first and second transistors (Tl, T2) to conduct and operable in the second state to cause only the third and fourth transistors (T3, T4) to conduct, said one set of amplifier inputs (3.2, 3.1) being the base connections to the first and second transistors (Tl, T2) and said other set of amplifier inputs (2.2, 2.1) being the base connections to the third and fourth transistors (T3, T4), said circuit input (5) being directly connected to the amplifier inputs (3.2, 2.1) to the first and fourth transistors (TI, T4) and the circuit output (6) being coupled through a current to voltage converter (T14-T20, R9 - R10) to the emitter/collector paths of said second and fourth transistors (T2, T4), the amplifier input (2.2) to said third transistor (T3) being directly connected to a first reference voltage (ground), and the amplifier input (3.1) to the second transistor (T2) being directly connected to the circuit output (6), a first feedback resistor (R1) connected between the circuit input (5) and said first reference voltage (ground) and a second feedback resistor (R2) connected between the circuit input (5) and the circuit output (6), the arrangement being such that with said first and second transistors (Tl, T2) conducting, said amplifier operates in non-inverting mode with its gain defined by said first feedback resistor (R1) and with said third and fourth transistors (T3, T4) conducting, said amplifier operates in inverting mode with its gain defiend by said second feedback resistor (R2) .

Claim 4

A circuit as claimed in claim 2, in which said bistable switch consists of a fifth and sixth transistor long-tailed pair configuration (T5, T6), said fifth transistor (T5) being connected as the tail of said first and second transistor long-tailed pair configuration (Tl, T2) and said sixth transistor (T6) being connected as the tail of said third and fourth long-tailed pair configuration (T3, T4), the alternate states of the bistable switch, wherein one transistor is conducting and the other non-conducting, being determined by the relative levels of voltages applied to the bases of the transistors (T5, T6), and the nominal current through the two transistors (TI, T2 or T3, T4) of the selected long-tailed pair configuration of the amplifier being determined by a constant current source (T7, R3) connected as the tail of the long-tailed pair configuration (T5, T6) of the bistable switch.

Claim 5

A circuit as claimed in claim 3, in which the base of the sixth transistor (T6) is connected to a predetermined reference voltage (Vref) and a switching voltage (V) derived from said polarity select signal, and having a value either above or below said reference voltage (V ref ), is applied to the base of said fifth transistor (T5).

Claim 6

A circuit as claimed in claim 2, in which said current-to-voltage converter comprises a current mirror circuit (T14-T17, R8) operable to mirror emitter/collector current of said second and fourth transistors (T2, T4) into a constant current source (T18, R9), the current requirements of which correspond to the nominal emitter/collector current of said second or fourth transistors when conducting, a voltage being derived therefrom proportional to variations in nominal emitter/collector current (II) caused by an input current (I. ) at said input (5) and said voltage being amplified and supplied at said output voltage (Vo) to said circuit output (6).

Claim 7

A circuit as claimed in any one of the preceding claims in which the first and second feedback resistors (Rl, R2) are of identical value.