Patent EP0087979A2 successfully refreshed from Google Patents.
EP0087979A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A semiconductor memory device
Assignee: Fujitsu Ltd
•
Filing: 1983-03-02
•
Granted: —
•
Expires: 2003-03-02
Abstract
Abstract A static-type semiconductor memory device having a three-layer structure; the gate-electrode wiring lines being formed by a first conductive layer of, for example, polycrystalline silicon; the word lines, the ground lines, and the power supply lines being formed by a second conductive layer of, for example, aluminum; and the bit lines being formed by a third conductive layer of, for example, aluminum; the bit lines extending in a column direction, and the ground lines extending in a row direction; whereby an improved integration degree, an improved operating speed, an improved manufacturing yield, and a countermeasure for soft errors due to alpha particles are attained.
Inventors
- 👤 Keizo Aoyama
- 👤 Takahiko Yamauchi
- 👤 Teruo Seki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 21:44
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/063; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125; G11C5/005; G11C5/14; H; H10; H10B; H10B10/00; H10B10/15; H10W; H10W42/00; H10W42/20; H10W42/25; Y; Y10; Y10S; Y10S257/00; Y10S257/927
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
217 words
A semiconductor memory device comprising: a semiconductor substrate; a group of word lines formed on and insulated from said semiconductor substrate; a group of pairs of bit lines formed on and insulated from said semiconductor substrate; a group of power supply lines formed on and insulated from said semiconductor substrate; a group of ground lines formed on and insulated from said semiconductor substrate; a plurality of static-type memory cells consisting of MIS transistors cross-coupled with each other, each of said memory cells being provided at a cross point between one of said word lines and one of said pairs of bit lines, each of said memory cells having a gate electrode; and a plurality of gate-electrode wiring lines connected to the gate electrodes of said MIS transistors; characterized in that; said gate-electrode wiring lines are formed by a first conductive layer formed, through a first insulating layer, on said semiconductor substrate; at least one group, among said group of word lines, said group of power supply lines, and said group of ground lines, is formed by a second conductive layer formed, through a second insulating layer, on said first conductive layer; and said group of pairs of bit lines is formed by a third conductive layer formed, through a third insulating layer, on said first conductive layer.
Claim 2
Dependent Claim
217 words
A semiconductor memory device comprising: a semiconductor substrate; a group of word lines formed on and insulated from said semiconductor substrate; a group of pairs of bit lines formed on and insulated from said semiconductor substrate; a group of power supply lines formed on and insulated from said semiconductor substrate; a group of ground lines formed on and insulated from said semiconductor substrate; a plurality of static-type memory cells consisting of MIS transistors cross-coupled with each other, each of said memory cells being provided at a cross point between one of said word lines and one of said pairs of bit lines, each of said memory cells having a gate electrode; and a plurality of gate-electrode wiring lines connected to the gate electrodes of said MIS transistors; characterized in that; said gate-electrode wiring lines are formed by a first conductive layer formed, through a first insulating layer, on said semiconductor substrate; at least one group, among said group of word lines, said group of power supply lines, and said group of ground lines, is formed by a second conductive layer formed, through a second insulating layer, on said first conductive layer; and said group of pairs of bit lines is formed by a third conductive layer formed, through a third insulating layer, on said first conductive layer.
Claim 3
Dependent Claim
40 words
A semiconductor memory device as set forth in claim 1, " wherein said at least one group of lines formed by said second conductive layer extends in a row direction perpendicular to the extending column direction of said bit lines.
Claim 4
Dependent Claim
31 words
A semiconductor memory device as set forth in claim 2, wherein all of said word lines, said power supply lines, and said ground lines are formed by said second conductive layer.
Claim 5
Dependent Claim
49 words
A semiconductor memory device as set forth in claim 3, wherein said first conductive layer has a first resistivity; said second conductive layer has a second resistivity lower than or equal to said first resistivity; and said third conductive layer has a third resistivity lower than said first resistivity.
Claim 6
Dependent Claim
46 words
A semiconductor memory device as set forth in claim 4, wherein, said first conductive layer is a polycrystalline-silicon layer; and second conductive layer is a tungsten layer, a molybdenum layer, an aluminum layer, or a polycrystalline-silicon layer; and said third conductive layer is an aluminum layer.
Claim 7
Dependent Claim
24 words
A semiconductor memory device as set forth in claim 2, wherein said group of said ground lines is formed by said second conductive layer.
Claim 8
Dependent Claim
32 words
A semiconductor memory device as set forth in claim 6, wherein each of said ground lines is formed to cover at least a part of the drain regions of said MIS transistors.
Claim 9
Dependent Claim
42 words
A semiconductor memory device as set forth in claim 7, wherein each of said ground lines has a width smaller than the distance between two adjacent word lines and larger than the distance between two adjacent gate--electrode wiring lines in each row.
Claim 10
Dependent Claim
47 words
A semiconductor memory device as set forth in claim 3, further comprising a group of ground-line short--circuiting lines formed by said third conductive layer, each of said ground-line short-circuiting lines extending through said memory cells arranged in predetermined columns, and being in contact with said ground lines.
Claim 11
Dependent Claim
29 words
A semiconductor memory device as set forth in claim 9, wherein one of said ground-line shot-circuiting lines is provided to extend through the left-most column of the memory cells.
Claim 12
Dependent Claim
29 words
A semiconductor memory device as set forth in claim 9, wherein one of said ground-line short-circuiting lines is provided to extent through the right-most column of the memory cell.
Claim 13
Dependent Claim
28 words
A semiconductur memory device as set forth in claim 9, wherein said second conductive layer is a polycrystalline-silicon layer and said third conductive layer is an aluminum layer.
Claim 14
Dependent Claim
166 words
A semiconductor device comprising: a plurality of circuit units arranged in a matrix in a first direction and in a second direction; a group of first wiring lines for supplying power supply voltages or signals to said circuit units, connected to the circuit units arranged in said first direction and formed by a first conductive layer; a group of second wiring lines, for supplying power supply voltage or signals to said circuit units, crossing with said first wiring lines at predetermined distances on said first wiring lines, formed by a second conductive layer having a resistivity lower than the resistivity of said first conductive layer, and extending in said second direction; and contact portions provided at cross portions between said first wiring lines and said second wiring lines, for short-circuiting between said first wiring lines and said second wiring lines; characterized in that; each of said second wiring lines extends through the inside of said circuit units arranged in one column extending in said second direction.
Claim 15
Dependent Claim
166 words
A semiconductor device comprising: a plurality of circuit units arranged in a matrix in a first direction and in a second direction; a group of first wiring lines for supplying power supply voltages or signals to said circuit units, connected to the circuit units arranged in said first direction and formed by a first conductive layer; a group of second wiring lines, for supplying power supply voltage or signals to said circuit units, crossing with said first wiring lines at predetermined distances on said first wiring lines, formed by a second conductive layer having a resistivity lower than the resistivity of said first conductive layer, and extending in said second direction; and contact portions provided at cross portions between said first wiring lines and said second wiring lines, for short-circuiting between said first wiring lines and said second wiring lines; characterized in that; each of said second wiring lines extends through the inside of said circuit units arranged in one column extending in said second direction.
Claim 16
Dependent Claim
38 words
A semiconductor device as set forth in claim 13, wherein said circuit units are static-type memory cells; said first lines are ground lines formed by polycrystalline silicon; and said second lines are ground-line short--circuiting lines formed by aluminum.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.