Patent EP0087368A2 successfully refreshed from Google Patents.
EP0087368A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Interchangeable interface circuit structure
Assignee: Digital Equipment Corp
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Filing: 1983-02-21
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Granted: —
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Expires: 2003-02-21
Abstract
Abstract The present disclosure describes an interface circuit arrangement which per se includes: a means for being addressed in accordance with its physical location, a means to generate signals which identify the circuit being addressed; and means to generate signals which effect a diagnostic routine of the circuit being addressed. The present disclosure further describes means, which operate in conjunction with a data handling system, to assert a priority value assigned to the interchangeable interface circuit and which, based on that priority, determines which one of a number of interchangeable interface circuits will be permitted to control a common data path.
Inventors
- 👤 Ronald A. Caprio
- 👤 John P. Cyr
- 👤 Bernard Geaghan
- 👤 Paul C. Kotschenreuter
- 👤 David J. Schanin
- 👤 Ronald M. Salett
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 22:09
CPC Classifications
G; G06; G06F; G06F3/00; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/30; G06F13/36; G06F13/368; G06F13/378
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
190 words
Interface circuitry means for connecting data signal handling circuitry to data signal responsive means, wherein said data signal handling circuitry has a plurality of sets of option circuit terminals formed for engagement with associated portions of each of a. plurality of interface circuitry means and wherein at least one option circuit terminal of each set is responsive to associated address data signals to identify its location, characterized by in combination; circuitry mounting means formed to enable portions of circuitry mounted thereon to be moved into engagement with associated ones of said option circuit terminals; first circuitry means, mounted on said circuitry mounting means, formed to have portions thereof engage first ones of said option terminals and further formed to provide signals to said data signal handling means to identify which one of said plurality of interface circuitry means is mounted on said circuitry mounting means; and second circuitry, mounted on said circuitry mounting means, formed to be connected to said first circuitry means and to an associated data signal responsive means whereby data signals can be transmitted between said data signal handling circuitry and said associated data signal responsive means.
Claim 2
Dependent Claim
190 words
Interface circuitry means for connecting data signal handling circuitry to data signal responsive means, wherein said data signal handling circuitry has a plurality of sets of option circuit terminals formed for engagement with associated portions of each of a. plurality of interface circuitry means and wherein at least one option circuit terminal of each set is responsive to associated address data signals to identify its location, characterized by in combination; circuitry mounting means formed to enable portions of circuitry mounted thereon to be moved into engagement with associated ones of said option circuit terminals; first circuitry means, mounted on said circuitry mounting means, formed to have portions thereof engage first ones of said option terminals and further formed to provide signals to said data signal handling means to identify which one of said plurality of interface circuitry means is mounted on said circuitry mounting means; and second circuitry, mounted on said circuitry mounting means, formed to be connected to said first circuitry means and to an associated data signal responsive means whereby data signals can be transmitted between said data signal handling circuitry and said associated data signal responsive means.
Claim 3
Dependent Claim
68 words
Interface circuitry means as in Claim 1, characterized in that said first circuitry means includes data signal generating means which are formed to provide diagnostic routine instruction signals to said data signal handling means whereby at a selected time said data signal handling means can transmit signals to said interface circuitry means to effect diagnostic tests on selected portions of the circuitry mounted on said circuitry mounting means.
Claim 4
Dependent Claim
51 words
Interface circuitry means as in Claim 2, characterized in that said first circuitry means also includes an address register and a signal means connected thereto whereby address signals transmitted from said data signal handling means are temporarily held and then decoded to provide contral signals to said data signal generating means.
Claim 5
Dependent Claim
73 words
Interface circuitry means as in Claim 1, characterized in that one of said portions of said first circuitry means comprises an address circuit terminal disposed to engage any of said at least one option circuit terminals of said sets of option circuit terminals to condition said first-circuitry means to be operative, in response to address data signals associated with said at least one option circuit terminal which said address circuit terminal is engaged.
Claim 6
Dependent Claim
95 words
Interface circuitry means as in Claim 1, characterized in that two of said option circuit terminals of said data signal handling circuitry are formed to be part of an option present circuit and further wherein said first circuitry means includes two engaging option present terminals to engage said two option present terminals of said data signal handling circuitry to provide an option present signal when said terminals are so engaged, indicating to the data signal handling circuitry that there is a circuitry mounting means in engagement at the position identified by said option present signal.
Claim 7
Dependent Claim
95 words
Interface circuitry means as in Claim 4, characterized in that said first circuitry means includes first strobe signal means adapted to be connected to one of said option circuit terminals to receive a first strobe signal from said data signal handling circuitry; first logic circuitry connected to said address cirucit terminal and to said first strobe signal means to generate a reply signal in response to the simultaneous presence of a strobe signal and a signal on said address circuit terminal indicating to said data signal handling circuitry that the interface circuitry has been addressed.
Claim 8
Dependent Claim
34 words
Interface circuitry means as in Claim 6, characterized in that there is further included signal delay means connected between said first data strobe means and said first logic circuitry to delay said reply signal.
Claim 9
Dependent Claim
51 words
Interface circuitry means as in Claim 2, characterized in that said data signal generating means is a read only memory and wherein there is further included a counter circuit connected to said read only memory to activate each address of said read only memory in response to said counter being incremented.
Claim 10
Dependent Claim
36 words
Interface circuitry means as in Claim 1, characterized in that said first circuitry means includes a data register connected to said second circuitry to receive and store data signals from an associated data signal responsive means.
Claim 11
Dependent Claim
77 words
Interface circuitry means as in Claim 1, characterized in that said first circuitry includes a means for generating a request for control of a data flow path in said data signal handling circuitry and wherein there is further included priority determination circuitry adapted to be on other interface citcuitry means whereby such priority determination circuitry will contribute to determining the priority among interface circuit cards so connected with respect to having control of said data flow path.
References Cited (Backward Citations)
No citation records indexed.
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