Patent EP0087367A2 successfully refreshed from Google Patents.
EP0087367A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Interchangeable interface circuitry arrangements for use with a data processing system
Assignee: Digital Equipment Corp
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Filing: 1983-02-21
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Granted: —
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Expires: 2003-02-21
Abstract
Abstract The present disclosure is directed to an arrangement whereby any one of a plurality of different or similar interface circuit cards can be located into any one of a number of slots or holding means of a data processing system, without preassignment thereto, and whereby each of the interface circuit cards will generate its own diagnostic routine signals and signals representing its own identification, the latter signals being used in a self-configuration operation of the system and whereby an arbiter means is employed to determine, amongst the plurality of interface circuits, which has the highest priority in the event more than one of said interface circuits is requesting the use of a common data flow path.
Inventors
- 👤 Equipment Corporation Digital
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 10:41
CPC Classifications
G; G06; G06F; G06F13/00; G06F11/00; G06F11/22; G06F11/2289; G06F11/006; G06F11/26; G06F11/273; G06F11/277; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F13/14; G06F13/20; G06F13/28; G06F13/30; G06F13/36; G06F13/368; G06F13/374; G05; G05B; G05B2219/00; G05B2219/20; G05B2219/25; G05B2219/25092
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
303 words
In association with a data processing system, which includes central processor circuitry means, memory circuitry means, control logic circuitry means and bus circuitry interconnecting the three last mentioned circuitry means characterized by means for enabling said data processing means to interchangeably utilize any one of a plurality of data signal responsive means, said means for enabling comprising in combination: a plurality of circuit mounting means each formed to have at least one interface circuit mounted thereon; a plurality of holding means each formed to enable any of said circuit mounting means to be interchangeably engaged with any of said holding means, each of said holding means being further formed to have engageable electrical terminals connected to said bus circuitry with at least one of said terminals being an address terminal; first circuitry coupled through said bus circuitry to said memory circuitry means and formed to receive and decode sets of address signals therefrom and wherein each set of address signals designates a different one of said holding means; second circuitry disposed to couple said first circuitry through said bus circuitry with each of said address terminals of said holding means whereby each of said address terminals will be respectively activated when a decoded set of address signals designates its holding means; a plurality of interface circuits each formed to have engaging electrical terminals and each disposed on a different one of said circuit mounting means and further disposed in engaging relationship with said engageable terminals of an associated holding means to be thereby connected to said bus circuitry and each formed to be connected to an associated one of said data signal responsive means, and each further formed to provide identifying signals to said data processing means to identify which one of said interface circuits is located at a holding means being addressed.
Claim 2
Dependent Claim
303 words
In association with a data processing system, which includes central processor circuitry means, memory circuitry means, control logic circuitry means and bus circuitry interconnecting the three last mentioned circuitry means characterized by means for enabling said data processing means to interchangeably utilize any one of a plurality of data signal responsive means, said means for enabling comprising in combination: a plurality of circuit mounting means each formed to have at least one interface circuit mounted thereon; a plurality of holding means each formed to enable any of said circuit mounting means to be interchangeably engaged with any of said holding means, each of said holding means being further formed to have engageable electrical terminals connected to said bus circuitry with at least one of said terminals being an address terminal; first circuitry coupled through said bus circuitry to said memory circuitry means and formed to receive and decode sets of address signals therefrom and wherein each set of address signals designates a different one of said holding means; second circuitry disposed to couple said first circuitry through said bus circuitry with each of said address terminals of said holding means whereby each of said address terminals will be respectively activated when a decoded set of address signals designates its holding means; a plurality of interface circuits each formed to have engaging electrical terminals and each disposed on a different one of said circuit mounting means and further disposed in engaging relationship with said engageable terminals of an associated holding means to be thereby connected to said bus circuitry and each formed to be connected to an associated one of said data signal responsive means, and each further formed to provide identifying signals to said data processing means to identify which one of said interface circuits is located at a holding means being addressed.
Claim 3
Dependent Claim
105 words
In association with a data processing means and a means for enabling as in Claim 1, characterized in that said data processing means has at least one data flow path which may be needed by various ones of said interface circuits in the course of operation and wherein more than one of said interface circuits is formed to have priority determination circuitry and wherein said one or more priority determination circuitries are connected together and are formed to determine from among said interface circuits which has the highest priority to enable such interface circuit to be temporarily in control of said needed data flow path.
Claim 4
Dependent Claim
96 words
In association with a data processing means and a means for enabling as in Claim 2, characterized in that said more than one interface circuits each have a priority value, and wherein there is further included arbiter circuitry means coupled to said more than one priority determining circuitry means and formed to determine which from among said more than one interface circuits shall be temporarily in control of said needed data flow path in the event that after said priority determination has been made, there is more than one interface circuit having the same priority value.
Claim 5
Dependent Claim
87 words
In association with a data processing means and a means for enabling as in Claim 1, characterized in that the further inclusion of self-configuring circuitry comprising instruction circuitry means coupled to said memory circuitry means through said bus and formed to provide signals to cause said memory circuitry means to store at an address, determined in part by a set of said identifying signals, a set of address signals which represent the address of the holding means whereat the interface circuit providing said identifying signals is located.
Claim 6
Dependent Claim
110 words
In association with a data processing means and means for enabling as in Claim 1, characterized in That the further inclusion, as part of each interface circuit, of diagnostic memory circuitry means which are formed to have a diagnostic routine stored therein, which routine is particularly directed to the interface circuit of which it is a part, and wherein each diagnostic memory means is formed to provide instruction data signals to said data processing means whereby said data processing means can cause certain different tests to be performed respectively on each of said interface circuits in accordance with said instruction data signals provided by each said diagnostic memory circuitry means.
Claim 7
Dependent Claim
97 words
In association with a data processing means and means for enabling, as in Claim 1, characterized in that the further inclusion of a plurality of option present circuits, wherein at least one different one of said option present circuits is associated with a different holding means and is designed to be activated when one of said interface circuits is engaged with its associated holding means electrical terminals and the further inclusion of register means connected to said option present circuits to provide signals to said data processing means to indicate which of said interface circuits is present.
Claim 8
Dependent Claim
93 words
In association with a data processing means and a means for enabling as in Claim 2, characterized in that each of said interface circuits has a priority value and the priority determination circuitry is formed to generate a demand for control signal, and wherein there is further included a "last look" circuit, which is formed to prevent said enabling of control of said needed data flow path after said demand for control signal has been generated, in the event that an interface of higher priority demands control of said needed data flow path.
Claim 9
Dependent Claim
67 words
In association with a data processing means and a means for enabling as in Claim 7, characterized in that said "last look" circuit is further formed to continually monitor the demands of circuits having higher priority and formed to terminate controlling said needed data flow path, even after said control has been granted, in the event of a demand for control by a circuit having higher priority.
Claim 10
Dependent Claim
60 words
In association with a data processing means and a means for enabling as in Claim 2, characterized in that there is further included a programmable means as part of said priority determination circuitry which is formed to effect a priority value for the interface circuit of which it is made a part in accordance with program generated input signals thereto.
Claim 11
Dependent Claim
224 words
In association with a data processing means which includes central processor circuitry means, memory circuitry means, control logic circuitry means and bus circuitry interconnecting the three last mentioned circuitry means characterized by means for enabling said data processing means to interchangeably utilize any ones of a plurality data signal responsive means, said means for enabling comprising in combination: a plurality of circuit mounting means each formed to have at least one interface circuit mounted thereon and each of said interface circuits formed to have engaging electrical terminals and at least one said engaging electrical terminals being part of an option present circuit; holding means formed to have engageable electrical terminals to enable any of said circuit mounting means to be interchangeably engaged therewith, said holding means being further formed to have at least one of said engageable electrical terminals being part of an option present circuit; option present circuitry connected to said at least one of said engaging electrical terminals and to said at least one of said engageable terminals to be activated when the engageable electrical terminals of said holding means engage a set of engaging electrical terminals of any one of said circuit mounting means to cause an option present signal to be generated, indicating that there is a data signal responsive means electrically disposed for use with said data processing means.
Claim 12
Dependent Claim
224 words
In association with a data processing means which includes central processor circuitry means, memory circuitry means, control logic circuitry means and bus circuitry interconnecting the three last mentioned circuitry means characterized by means for enabling said data processing means to interchangeably utilize any ones of a plurality data signal responsive means, said means for enabling comprising in combination: a plurality of circuit mounting means each formed to have at least one interface circuit mounted thereon and each of said interface circuits formed to have engaging electrical terminals and at least one said engaging electrical terminals being part of an option present circuit; holding means formed to have engageable electrical terminals to enable any of said circuit mounting means to be interchangeably engaged therewith, said holding means being further formed to have at least one of said engageable electrical terminals being part of an option present circuit; option present circuitry connected to said at least one of said engaging electrical terminals and to said at least one of said engageable terminals to be activated when the engageable electrical terminals of said holding means engage a set of engaging electrical terminals of any one of said circuit mounting means to cause an option present signal to be generated, indicating that there is a data signal responsive means electrically disposed for use with said data processing means.
Claim 13
Dependent Claim
161 words
Circuitry means for determining the priority amongst a group of circuits each of which has a priority value and each of which is formed to receive a demand for priority signal characterized by the combination of: at least two signal lines formed to carry voltage signals, with each line representing a data bit and when viewed together, representing at least three possible priority values and disposed so that each of said group of circuits is connected to at least one of said signal lines; first logic circuitry, disposed to be part of each of first ones of said group of circuits, coupled to a first one of said signal lines to receive a preempt signal therefrom should a second or third one of said group of circuits apply a signal to said first one of said signal lines, whereby a demand for priority signal, if received by any of said first ones of said group of circuits, would be rendered ineffective.
Claim 14
Dependent Claim
161 words
Circuitry means for determining the priority amongst a group of circuits each of which has a priority value and each of which is formed to receive a demand for priority signal characterized by the combination of: at least two signal lines formed to carry voltage signals, with each line representing a data bit and when viewed together, representing at least three possible priority values and disposed so that each of said group of circuits is connected to at least one of said signal lines; first logic circuitry, disposed to be part of each of first ones of said group of circuits, coupled to a first one of said signal lines to receive a preempt signal therefrom should a second or third one of said group of circuits apply a signal to said first one of said signal lines, whereby a demand for priority signal, if received by any of said first ones of said group of circuits, would be rendered ineffective.
Claim 15
Dependent Claim
168 words
Circuitry means for determining the priority amongst a group of circuits as in Claim 11, characterized in that there is further included second logic circuitry, disposed on each one of second ones of said group of circuits, coupled to a second one of said signal lines to receive a preempt signal therefrom should third ones of said group of circuits apply a signal to said second one of said signal lines, whereby a demand for priority signal, if received by said second ones of said group of circuits, would be rendered ineffective and whereby there is further included third logic circuitry means coupled to said second logic circuitry means and to said first one of said signal lines, whereby if there is no preempt signal from said second signal line and said demand for priority signal is received said third logic circuitry will apply a signal to said first signal line to provide preempt signals to any of said first ones of said group of circuits connected thereto.
Claim 16
Dependent Claim
104 words
Circuitry means for determining priority amongst a group of circuits as in Claim 12, characterized in that there is fourth logic circuitry and second logic circuitry coupled to said fourth logic circuitry, disposed to be connected to each one of third ones of said group of circuits, and coupled to said first and second ones of said signal lines to apply signals thereto in response to the receipt of a demand for priority signal whereby preempt signals will be transmitted to any of said first ones of said group of circuits and any of said second ones of said group of circuits connected thereto.
References Cited (Backward Citations)
No citation records indexed.
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