Source voltage build-up detecting circuit

Claim 1

A source voltage build-up detecting circuit which detects, after the source is switched on, whether the source voltage (V cc ) between a high potential line and a low potential line is higher than a predetermined voltage and outputs a detecting signal, comprising a level shifting element (TR16) which is conected to the high potential line (V cc ) and supplies a voltage lower than the source voltage to a complementary metal oxide semiconductor (CMOS) inverter as a working voltage, the inverter comprising a first P channel transistor (TR 2 ) and a first N channel transistor (TR 3 ) which are connected in series between the level shifting element (TR16) and the low potential line, the gates of the transistors being connected together; a second P channel transistor (TR 4 ) and a second N channel transistor (TR s ) which are connected in series between the high potential line and the low potential line, the series connection point between these transistors providing the output node (D) of the detecting circuit, and the gates of these transistors being connected to a series connection point (C) between the first P channel transistor and the first N channel transistor; and a voltage generating circuit (Ca, TR, 4 , TR 15 , TR,) which is connected between the high potential line and the low potential line, the output voltage of the voltage generating circuit being supplied to the gates of the first P channel transistor and the first N channel transistor to supply thereto, when the source voltage is lower than the predetermined voltage after the source voltage is switched on, a voltage which is higher than the threshold voltage of the CMOS inverter, and when the source voltage becomes higher than the predetermined voltage,. a voltage which is lower than the threshold voltage of the CMOS inverter, whereby when the source voltage reaches the predetermined value, the output of the CMOS inverter is inverted.