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EP0086601A2
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Multiprocessor system having mutual exclusion control function
Assignee: Toshiba Corp
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Filing: 1983-02-03
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Granted: —
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Expires: 2003-02-03
Abstract
Abstract A multiprocessor system includes a plurality of processors (10-1 to 10-N) which are respectively connected to a memory device (3) and each of which produces a first control signal when executing a test-and-set instruction and a second control signal after executing a sequence of queuing steps. The multiprocessor system further has flip-flop circuits (12-1 to 12-N) each of which is set in response to the first control signal from the corresponding one of the processors (10-1 to 10-N) and which are commonly reset in response to a second control signal from any one of the processors (10-1 to 10-N). The processors (10-1 to 10-N) are prevented from executing the test-and-set instruction while the corresponding one of the flip-flop circuits (12-1 to 12-N) is set.
Inventors
- 👤 Akira Maeda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 05:01
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F9/00; G06F9/06; G06F9/46; G06F9/52; G06F9/526; G06F2209/00; G06F2209/52; G06F2209/521
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
194 words
A multiprocessor system having a mutual exclusion function, comprising a plurality of data processing means (10-1 to 10-N) to be commonly connected to a memory device (3) which has at least one memory area (7, 7-1 to 7-M) for storing a flag of test-and-set instruction, said data processing means (10-1 to 10-N) respectively producing a first signal when executing a test-and-set instruction, and a second signal after executing a sequence of processing operations, characterized by further comprising a plurality of state signal generating means (12-1 to 12-N) which are respectively connected to said plurality of data processing means (10-1 to 10-N), and each of which generates a first state signal in response to the first signal from a corresponding one of said plurality of data processing means (10-1 to 10-N) and a second state signal in response to the second signal from any one of said plurality of data processing means (10-1 to 10-N), and characterized in that each of said plurality of data processing means (10-1 to 10-N) is prevented from executing the test-and-set instruction. while said corresponding one of said state signal generating means (12-1 to 12-N) generates the first state signal.
Claim 2
Dependent Claim
194 words
A multiprocessor system having a mutual exclusion function, comprising a plurality of data processing means (10-1 to 10-N) to be commonly connected to a memory device (3) which has at least one memory area (7, 7-1 to 7-M) for storing a flag of test-and-set instruction, said data processing means (10-1 to 10-N) respectively producing a first signal when executing a test-and-set instruction, and a second signal after executing a sequence of processing operations, characterized by further comprising a plurality of state signal generating means (12-1 to 12-N) which are respectively connected to said plurality of data processing means (10-1 to 10-N), and each of which generates a first state signal in response to the first signal from a corresponding one of said plurality of data processing means (10-1 to 10-N) and a second state signal in response to the second signal from any one of said plurality of data processing means (10-1 to 10-N), and characterized in that each of said plurality of data processing means (10-1 to 10-N) is prevented from executing the test-and-set instruction. while said corresponding one of said state signal generating means (12-1 to 12-N) generates the first state signal.
Claim 3
Dependent Claim
99 words
A multiprocessor system according to claim 1, characterized in that each of said plurality of state signal generating means (12-1 to 12-N) comprises a flip-flop circuit, a first input terminal of which is connected to receive a first signal from said corresponding one of said plurality of data processing means (10-1 to 10- N ), and a second input terminal of which is connected to receive any one of second signals from said plurality of data processing means (10-1 to 10-N), a state of each of said flip-flop circuits being controlled in accordance with the first and second signals.
Claim 4
Dependent Claim
27 words
A multiprocessor system according to claim 2, characterized in that said first and second input terminals of said flip-flop circuits are set and reset input terminals, respectively.
Claim 5
Dependent Claim
79 words
A multiprocessor system according to claim 1, characterized in that each of said plurality of state signal generating means (12-1 to 12-N) comprises a flip-flop circuit which is set in a first state in response to the first signal from said corresponding one of said plurality of data processing means (10-1 to 10-N) and is set in a second state in response to the second signal from any one of said plurality of data processing means (10-1 to 10-N).
References Cited (Backward Citations)
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