Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
160 words
Apparatus for error correction, characterised by a data memory (37), a write address generator (38) on the basis of which data sequences containing blocks each formed of plural data words - previously arranged on a time-base - and check words are written into the data memory, a read address generator (39) on the basis of which the data sequences are read out from the data memory (37) so as to generate rearranged data sequences, and error correction means (40) operative to effect error correction during writing and reading of the data sequences, the error correction means (40) comprising an error correction arithmetic circuit (50; 50A) for performing an error correction calculation, a pointer addition circuit (51, 52) for adding a pointer to the data words in association with an error state of the blocks, and a program memory (49) for memorizing a microprogram with fields to control the error correction arithmetic circuit (50; 50A) and pointer addition circuit (51, 52).
Claim 2
Dependent Claim
160 words
Apparatus for error correction, characterised by a data memory (37), a write address generator (38) on the basis of which data sequences containing blocks each formed of plural data words - previously arranged on a time-base - and check words are written into the data memory, a read address generator (39) on the basis of which the data sequences are read out from the data memory (37) so as to generate rearranged data sequences, and error correction means (40) operative to effect error correction during writing and reading of the data sequences, the error correction means (40) comprising an error correction arithmetic circuit (50; 50A) for performing an error correction calculation, a pointer addition circuit (51, 52) for adding a pointer to the data words in association with an error state of the blocks, and a program memory (49) for memorizing a microprogram with fields to control the error correction arithmetic circuit (50; 50A) and pointer addition circuit (51, 52).
Claim 3
Dependent Claim
65 words
Apparatus according to claim 1, wherein the microprogram has a format (Figs. 9A, 9B) containing a branch field, a control field and a random access memory address field, and the branch field specifies the presence or absence of a jump and the condition thereof, whereby in a format with the possibility of such a jump, a part of the control field becomes a jump address.
Claim 4
Dependent Claim
139 words
Apparatus according to claim 1 or claim 2, wherein the error correction arithmetic circuit (50A) includes a galois field multiplication circuit (108, 109, 79, 83) in which, in use, parallel data of n bits making up an element A of a galois field GF (2 n ) is sequentially multiplied with each bit of serial data of n bits making up an element B of the galois field GF ( 2 n ), data of n bits resulting in turn from the multiplication are supplied to an adder and multiplied by a root J, of a generation polynomial of the galois field GF (2 n ), and data resulting from the multiplication are delayed by one bit each and fed back to the adder thereby to compute A x B on the galois field G F (2 n ).