Drive circuit for capacitive loads

Claim 2

An inverter circuit comprising a first field effect transistor (Q 11 ) of one conductivity type, a second field effect transistor of the opposite conductivity type (Q 12 ) connected with said first transistor in series between two power supply terminals, an input terminal (15) coupled to the gates of said first and second transistors, an output terminal (17) coupled to the connection point of said first and second transistors, for connection to a capacitive load, characterised by a capacitor (C A ), first means (Q 16 ) coupled to the capacitor and to one (16) of the said power supply terminals for charging the capacitor (C A ) at a time other than a transient period when a potential at the output terminal changes from a first level to a second level, and second means (Q 14 , Q 15 ) coupled to the capacitor and the output terminal for charging the capacitive load by a discharge current from the capacitor (C A ) during the transient period.

Claim 3

An inverter according to claim 1, characterised in that it further comprises third means (13) coupled to the one said power supply terminal (16) and the output terminal for charging the capacitive load by a current from the power supply during the said transient period after the discharge current from the capacitor (C A ) starts to flow.

Claim 4

An inverter according to claim 1, characterised in that the first means includes a first switch transistor (Q 16 ) and the second means includes a series connection circuit of a second and a third switch transistor (Q 15 , Q 14 ), the second switch transistor (Q 15 ) being controlled by the voltage (Ø OUT ) at the output terminal, and the third switch transistor (Q 14 ) being controlled by an input signal (Ø IN ) at the input terminal (15).

Claim 5

An inverter according to claim 2, characterised in that the third means include a delay circuit (14) for delaying an input signal received at the input terminal and a fourth switch transistor (Q 13 ) connected between the said one terminal (16) of the power supply and the output terminal (17).

Claim 6

An inverter comprising a basic inverter circuit (11) responsive to an input signal (Ø IN ) for sending out an output signal that is inverted relative to the input signal, characterised by a first auxiliary circuit (12) and a second auxiliary circuit (13) connected in parallel between an output terminal (17) of the basic inverter circuit and a power supply, respectively, the first auxiliary circuit (12) serving to discharge electric charge stored in an auxiliary capacitor (C A ) when the input signal is at "1" level or "0" level to the output terminal during a transient period when the input signal changes from a "1" level or "0" level, respectively, to "0" level or "1" level, respectively, the second auxiliary circuit (13) serving to feed a current to the output terminal of the basic inverter circuit in a predetermined period during the said transient period.

Claim 7

An inverter comprising a basic inverter circuit (11) responsive to an input signal (Ø IN ) for sending out an output signal that is inverted relative to the input signal, characterised by a first auxiliary circuit (12) and a second auxiliary circuit (13) connected in parallel between an output terminal (17) of the basic inverter circuit and a power supply, respectively, the first auxiliary circuit (12) serving to discharge electric charge stored in an auxiliary capacitor (C A ) when the input signal is at "1" level or "0" level to the output terminal during a transient period when the input signal changes from a "1" level or "0" level, respectively, to "0" level or "1" level, respectively, the second auxiliary circuit (13) serving to feed a current to the output terminal of the basic inverter circuit in a predetermined period during the said transient period.

Claim 8

An inverter according to claim 5, characterised in that the basic inverter circuit includes a first P-channel type field effect transistor (0 ) and a first N-channel type field effect transistor (Q 11 ) connected in series and inserted between the power supply terminal (16) and a ground terminal, the gates of the two transistors being connected in common to form an input terminal (15), and a common junction point of the two transistors being coupled to an output terminal (17), the first auxiliary -circuit (12) including second, third and fourth P-channel type field effect transistors (Q 16 , Q 15 , Q 14 ) connected in series with each other and having their gates connected respectively to the ground terminal, the output terminal and the input terminal, and an auxiliary capacitor (C A ) inserted between the common junction point of the second and third P-channel type field effect transistors (Q 16 , Q 15 ) and the ground terminal, the second auxiliary circuit including a fifth P-channel type field effect transistor (Q 13 ) having its gate connected via a delay circuit (14) to the input terminal (15).

Claim 9

An inverter according to claim 6, characterised in that the said second auxiliary circuit includes a sixth P-channel type field effect transistor (Q 17 ) inserted between the fifth P-channel type field effect (Q 13 ) transistor and the output terminal (17) and having its gate connected to the input terminal (15).

Claim 10

A digital circuit with an output stage having an output terminal for driving a capacitive load, characterised by a capacitor (C A ), first means (Q16) coupled to the capacitor and to one (16) of the power supply terminals for charging the capacitor (C A ) at a time other than a transient period when a potential at the output terminal changes from a first level to a second level, and second means (Q 14 , Q 15 ) coupled to the capacitor and the output terminal for charging the capacitive load by a discharge current from the capacitor (C A ) during the transient period.

Claim 11

A digital circuit with an output stage having an output terminal for driving a capacitive load, characterised by a capacitor (C A ), first means (Q16) coupled to the capacitor and to one (16) of the power supply terminals for charging the capacitor (C A ) at a time other than a transient period when a potential at the output terminal changes from a first level to a second level, and second means (Q 14 , Q 15 ) coupled to the capacitor and the output terminal for charging the capacitive load by a discharge current from the capacitor (C A ) during the transient period.