Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
188 words
In a buffer circuit for producing two output signals (A o , A o ) of the opposite phases in response to an input signal (A I ) comprising a pre-circuit (1) producing two pre-output signals (A' o , A' o ) in accordance with said input signal (A I ) and a reference voltage signal (V REF ); and a main circuit (2) including a latch circuit (Q 17 , Q 18 ) latching said pre-output signals (A' o , A' o ), and a flip-flop circuit (Q 11 , Q 12 ) connected to receive said pre-output signals (A' o , A' o ) latched by said latch circuit (Q 17 , Q 18 ) for producing the output signals (A o , A o ) of the buffer circuit, the improvement wherein said main circuit (2) comprises a transfer gate circuit (Q 13 , Q 14 , Q 15 , Q 16 , C 3 , C 4 ) enabled by said pre-output signals (A' o , A' o ) and disabled by said output signals (A , A o ) of the buffer circuit.
Claim 2
Dependent Claim
188 words
In a buffer circuit for producing two output signals (A o , A o ) of the opposite phases in response to an input signal (A I ) comprising a pre-circuit (1) producing two pre-output signals (A' o , A' o ) in accordance with said input signal (A I ) and a reference voltage signal (V REF ); and a main circuit (2) including a latch circuit (Q 17 , Q 18 ) latching said pre-output signals (A' o , A' o ), and a flip-flop circuit (Q 11 , Q 12 ) connected to receive said pre-output signals (A' o , A' o ) latched by said latch circuit (Q 17 , Q 18 ) for producing the output signals (A o , A o ) of the buffer circuit, the improvement wherein said main circuit (2) comprises a transfer gate circuit (Q 13 , Q 14 , Q 15 , Q 16 , C 3 , C 4 ) enabled by said pre-output signals (A' o , A' o ) and disabled by said output signals (A , A o ) of the buffer circuit.
Claim 3
Dependent Claim
146 words
A buffer circuit according to claim 1 wherein said main circuit (2) comprises a control circuit responsive to said pre-output signal (A' o , A' o ) to disable, in the presence of a clock signal (P 1 ) for pre-charging the output nodes (N 7 , N 8 ) of the main circuit (2), the transfer gate circuit (Q 13 , Q 14 , Q 15 , Q 16 , C 3 , C 4 ) when said input signal (A I ) and reference voltage (V REF ) are of the same leval and enable, in the absence of the pre-charging clock signal (P 1 ), the transfer gate circuit (Q 13 , Q 14' Q 15 , Q 16 , C 3 ' C 4 ) when said input signal (A I ) and reference voltage (V REF ) are of different levels.
Claim 4
Dependent Claim
205 words
A buffer circuit according to claim 1 wherein said transfer circuit (Q 13 , Q 14 , Q 15' Q 16' C 3' C 4 ) com - prises a first pair of field effect transistors (Q 13 , Q14) with their source electrodes connected to one output node (N 7 ) and the other output node (N 8 ) of the main circuit (2), respectively, and gate electrodes connected to said the other node (N 8 ) and said one node (N 7 ); a second pair of field effect transistors (Q 15 , Q16) with their source electrodes connected to the drain electrodes of the first pair of field effect transistors (Q 13 , Q14), drain electrodes connected to receive said pre-output signals (A', A' o ), and gate electrodes connected to the gate electrodes of the first pair of field effect transistors (Q 13 , Q 14 ); and bootstrap capacitors (C 3 , C 4 ) respectively connected to the node (N 9 , N 10 ) between the drain electrode of the first pair of field effect transistors (Q13' Q 14 ) and the source electrode of the second pair of field effect transistors (Q 15 , Q 16 ).'