Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
314 words
An array processor characterized by: - a main storage unit (MS) for storing scalar data, vector data and array data and for separately storing scalar instruction series, vector- and array instruction series; - scalar instruction executing means (SP) for reading out said scalar instruction series and said scalar data from said main storage unit for decoding and executing said scalar instructions read out and for storing said scalar data obtained by said executions in said main storage unit; and - vector and array instruction executing means (VPC, PE) for reading out said vector instructions or array instruction series and said vector or array data of said main storage unit for decoding and executing said vector and array instructions read out and for storing said vector or array data obtained by said executions in said main storage unit, wherein said vector and array instruction executing means include: - main vector instruction executing means for executing vector instructions designating the operations of one-dimensional array data to obtain a one-dimensional array or scalar data and - a plurality of array instruction executing means (PE l - PE m ) for executing array instructions designating the operations of two-dimensional array data, each of said array instruction executive means (PE l - PE M ) being made operative to execute operations of one of a plurality of one-dimensional array data constructing said two-dimensional array data thereby to determine one element of one-dimensional array result data when said array instructions instruct that as result data said one-dimensional array result data are required and thereby to determine one of plural one-dimensional array result data constructing two-dimensional array result data, when said array instructions instruct that as result data said two-dimensional array result data are required, and - wherein said scalar instruction means include: - means for generating in response to said scalar instruction data necessary for vector and scalar instruction series.
Claim 2
Dependent Claim
314 words
An array processor characterized by: - a main storage unit (MS) for storing scalar data, vector data and array data and for separately storing scalar instruction series, vector- and array instruction series; - scalar instruction executing means (SP) for reading out said scalar instruction series and said scalar data from said main storage unit for decoding and executing said scalar instructions read out and for storing said scalar data obtained by said executions in said main storage unit; and - vector and array instruction executing means (VPC, PE) for reading out said vector instructions or array instruction series and said vector or array data of said main storage unit for decoding and executing said vector and array instructions read out and for storing said vector or array data obtained by said executions in said main storage unit, wherein said vector and array instruction executing means include: - main vector instruction executing means for executing vector instructions designating the operations of one-dimensional array data to obtain a one-dimensional array or scalar data and - a plurality of array instruction executing means (PE l - PE m ) for executing array instructions designating the operations of two-dimensional array data, each of said array instruction executive means (PE l - PE M ) being made operative to execute operations of one of a plurality of one-dimensional array data constructing said two-dimensional array data thereby to determine one element of one-dimensional array result data when said array instructions instruct that as result data said one-dimensional array result data are required and thereby to determine one of plural one-dimensional array result data constructing two-dimensional array result data, when said array instructions instruct that as result data said two-dimensional array result data are required, and - wherein said scalar instruction means include: - means for generating in response to said scalar instruction data necessary for vector and scalar instruction series.
Claim 3
Dependent Claim
160 words
An array processor according to claim 1, wherein said main vector instruction executing means include: - a plurality of first vector registers (VC1 - VCL), - a plurality of first scalar registers (SC1 - SCZ), - a first pipe-line operating means, - means for fetching said vector instructions of said array instructions, - means for decoding whether said fetched instructions are said vector instructions or said array instructions and for controlling said first vector registers, said first scalar registers and said first pipe-line operating means, when the decoded instructions are said vector instructions, thereby to execute said decoded vector instructions, - means for sending each element of said one-dimensional array data to corresponding one of said array instruction executing means when the computed results of said fetched vector instructions are said one-dimensional array data and - means for storing said element of said one-dimensional array data which has been computed by each of said plurality of array instruction executing means.
Claim 4
Dependent Claim
157 words
An array processor according to claim 1 and 2, characterized in that each of said array instruction processing means includes: - a plurality of second vector registers (V i l - V i K), - a plurality of second scalar registers (S i l - S . L), - a second pipe-line operating means, - means for controlling said second vector registers, said second scalar registers and said second pipe-line operating means, when said fetched instructions are said array instructions, thereby to execute said array instructions of the two-dimensional array data instructed by said fetched instructions which has been fetched for one of said one-dimensional array data, - means for sending one element of said one-dimensional array data to said main vector instruction executing means when the resultant data of said execution reduces to scalar data and - means for storing said one element sent out from said first means in one of said second scalar registers.
Claim 5
Dependent Claim
82 words
An array processor according to anyone of the preceeding claims, characterized in that each of said plural vector instruction executing means includes means for holding the vector length to be independently processed by each of said plural vector instruction execution means, the start address of the vector data of said main storage unit to be processed and the data increment of said vector data, all of which are to be transferred by said transfer means and for using them for controlling purposes.