Delta-sigma modulator with switched capacitor implementation

Claim 2

A DeLta-Sigma modulator for digitally encoding an analog input signal, characterized in that it comprises: - clock means (303) for generating a timing waveform (f) having a frequency substantially higher than the highest frequency component of said analog input signal; - a sampling circuit (1, 3, C 1 ) including switching capacitance means for storing charge representative of instantaneous amplitude values of said analog input signal (u(t)); - integrating means (4, C 3 ) operative as a lowpass filter responsive to the output of said sampling circuit (1, 3 , C 1 ); - a one-bit analog-to-digital converter (19, 20) clocked by said timing waveform (f s ) and providing first and second outputs (Q, Q) in response to the instantaneous polarity of the output signal of said integrating means (4, C 3 ), said second output (Q) being complementary of said first output (Q); - reference means (301) for selectively applying a charging voltage to said integrating means (4, C 3 ).

Claim 3

A DeLta-Sigma modulator as claimed in claim 1, characterized in that it further comprises: - a second sampling circuit including switching capacitance means (10, 12, C 4 ) for storing charge representative of instantaneous amplitude values of the output signal (X(nT)) of said first integrating means (4, C 3 ); - second integrating means (17, C 6 ) operative as a second Lowpass filter responsive to the output of said second sampling circuit (10, 12, C 4 ), said one-bit analog-to-digital converter (19, 20) being responsive to the output signal of said second integrating means (17, C 6 ) and - second reference means (302) for selectively applying a charging voltage to said second integrating means (17, C 6 ) (Fig. 3).

Claim 4

A DeLta-Sigma modulator as claimed in claims 1 or 2, characterized in that - said clock means (303) generate, in addition, to said timing waveform (f s ) having first and second levels, first and second switching gates (θ 1 ,θ 2 ) within the duration of, but not overlapping said timing gate waveform first and second levels; - said first and second sampling circuits (1, 3, C 1 , 10, 12, C 4 ) are each operated to store during said first switching gate (9 1 ) charge representative of the instantaneous amplitude value of their respective analog input signal and to output said stored charge during said second switching gate (θ 2 ), said first and second sampling circuits comprising first and second capacitors (C 1 , C 4 ) for charge storage and switching means associated therewith; - said first reference means (301) include a third capacitor (C 2 ) and additional switching means (6, 7, 9) connected to charge said third capacitor CC 2 ) to +V or -V reference voltage during said first switching gate (θ 1 ) in polarity corresponding to θ 1 nQ or θ 1 nQ, respectively, where θ 1 is said first switching gate and to apply said third capcitor voltage to said first integrating means input during said second switching gate (θ 2 ); - and said second reference means (302) include a fourth capacitor (C5) and second additional switching means (13, 14, 16) connected to charge said fourth capacitor (C 5 ) to + V or -V reference voltage during said first switching gate (θ 1 ) in polarity corresponding to θ 1 nQ or θ 1 n Q, respectively, and to apply said fourth capacitor voltage to said second integrating means input during said second switching gate (θ 2 ) (Fig. 3).

Claim 5

A DeLta-Sigma modulator as claimed in any one of the preceding claims, characterized in that said first and second integrators comprise corresponding inverting first and second operational amplifiers (4, 17) having fifth and sixth capacitors (C 3 , C 6 ), connected between input and output of said first and second amplifiers (4, 17), respectively (Fig. 3, Fig. 6).

Claim 6

A Delta-Sigmal modulator as claimed in any one of the preceding claims, characterized in that said one-bit analog-to-digital converter comprises a comparator (19) responding to the preceding integrator to provide a polarity responsive output having a first or second condition, and a D type flip-flop circuit (20) responsive to said comparator output for providing Q and Q outputs, said Q output providing the one-bit code (Fig. 3, Fig. 6).

Claim 7

A DeLta-Sigma modulator as claimed in claim 4, characterized in that the ratio of the capacitance of said first capacitor (C 1 ) to that of said fifth capacitor (C 3 ) and the capacitance ratio of said third capacitor (C 2 ) to that of said fifth capacitor (C 3 ) is approximately 1/2; the ratio of the capacitance of said second capacitor (C 4 ) to that of said sixth capacitor (C 6 ) and the capacitance ratio of said fourth capacitor (C 5 ) to that of said sixth capacitor ( C6 ) being unity (Fig. 3, Fig. 6).

Claim 8

A Delta-Sigma modulator as claimed in any one of the preceding claims, characterized in that said clock means (303) is further defined as generating said switching gates (θ 1 , e 2 ) each substantially time-centered with the duration of the corresponding timing gate waveform first and second LeveLs (Fig. 4).

Claim 9

A DeLta-Sigma modulator as claimed in any one of the preceding claims, characterized in that said first reference means (601) includes additional switching means (22, 24) associated with said third capacitor (7). for switching the terminal of said third capacitor (C 7 ) which is connected to ground potential to the positive terminal thereof during the time of θ 2 nQ and to the negative terminal thereof during θ 1 , said third capacitor voltage being outputted to said first integrating means (4, C 3 ) du-ring θ 2 nQ, said second reference means (602) comprising second additional switching means (30, 33) associated with said fourth capacitor (C 9 ) for switching the terminal thereof which is connected to ground potential to the positive terminal thereof during the time θ 2 nQ and to the negative terminal during θ 1 , said fourth capacitor voltage being outputted to said second integrating means (17, C 6 ) during θ 2 nQ, thereby to provide the function of said reference means using only a positive reference voltage (+V) (Fig. 5, Fig. 6).

Claim 10

A DeLta-Sigma modulator as claimed in any one of the preceding claims, characterized in that said switching means comprise individual signal controLLed electronic switches.