Patent EP0084000A2 successfully refreshed from Google Patents.
EP0084000A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
CMOS device
Assignee: Fairchild Semiconductor Corp
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Filing: 1983-01-04
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Granted: —
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Expires: 2003-01-04
Abstract
Abstract Latch-up in CMOS devices (11c) by conduction of parasitic bipolar transistors (29c, 30c) is prevented by providing a voltage drop between the power supply voltage (V' cc ) of the CMOS device and a voltage drop between the well region and ground. By providing these voltage drops, the parasitic transistors are prevented from conducting, and the channel lengths decreased, thus increasing current handling ability and decreasing switching times as compared with prior art CMOS devices.
Inventors
- 👤 Peter Cheng-Yu Chen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 23:04
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/205
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
203 words
A CMOS device comprising: a first terminal (14) for connection to a source of power; a second terminal (24) for connection to ground; a semiconductor substrate (11) of a first conductivity type connected to said first terminal; a well region (18) of a second conductivity type opposite said first conductivity type formed within said substrate; a first source region (13) and a first drain region (17) each of said second conductivity type formed within said substrate; a second source region (19) and a second drain region (21) each of said first conductivity type formed within said well region; a first gate electrode (16) located above the portion of said substrate between said first source and first drain regions, said first gate electrode being insulated from said substrate; a second gate electrode (20) located above the portion of said well re q ion between said second source and second drain regions, said second gate electrode being insulated from said well region; characterized by further comprising: a voltage drop means (31) connected between said first terminal and said first source region (13), said voltage drop means making said first source region less positive than said first terminal when power is applied to said CMOS device.
Claim 2
Dependent Claim
203 words
A CMOS device comprising: a first terminal (14) for connection to a source of power; a second terminal (24) for connection to ground; a semiconductor substrate (11) of a first conductivity type connected to said first terminal; a well region (18) of a second conductivity type opposite said first conductivity type formed within said substrate; a first source region (13) and a first drain region (17) each of said second conductivity type formed within said substrate; a second source region (19) and a second drain region (21) each of said first conductivity type formed within said well region; a first gate electrode (16) located above the portion of said substrate between said first source and first drain regions, said first gate electrode being insulated from said substrate; a second gate electrode (20) located above the portion of said well re q ion between said second source and second drain regions, said second gate electrode being insulated from said well region; characterized by further comprising: a voltage drop means (31) connected between said first terminal and said first source region (13), said voltage drop means making said first source region less positive than said first terminal when power is applied to said CMOS device.
Claim 3
Dependent Claim
191 words
A CMOS device comprising: a first terminal (14) for connection to a positive source of power; a second terminal (24) for connection to ground; a semiconductor substrate (11) of a first conductivity type connected to said first terminal; a well region (18) of a second conductivity type opposite said first conductivity type formed within said substrate; a first source region (13) and a first drain region (17) each of said second conductivity type formed within said substrate; a second source region (19) and a second drain region (21) each of said first conductivity type formed within said well region; a first gate electrode (16) located above the portion of said substrate between said first source and first drain regions, said first gate electrode being insulated from said substrate; a second gate electrode (20) located above the portion of said well region between said second source and second drain regions, said second gate electrode being insulated from said well region; characterized by further comprising: a voltage drop means (Vx) connected in series between said second terminal and said well region, said voltage source making said well region negative with respect to ground.
Claim 4
Dependent Claim
191 words
A CMOS device comprising: a first terminal (14) for connection to a positive source of power; a second terminal (24) for connection to ground; a semiconductor substrate (11) of a first conductivity type connected to said first terminal; a well region (18) of a second conductivity type opposite said first conductivity type formed within said substrate; a first source region (13) and a first drain region (17) each of said second conductivity type formed within said substrate; a second source region (19) and a second drain region (21) each of said first conductivity type formed within said well region; a first gate electrode (16) located above the portion of said substrate between said first source and first drain regions, said first gate electrode being insulated from said substrate; a second gate electrode (20) located above the portion of said well region between said second source and second drain regions, said second gate electrode being insulated from said well region; characterized by further comprising: a voltage drop means (Vx) connected in series between said second terminal and said well region, said voltage source making said well region negative with respect to ground.
Claim 5
Dependent Claim
36 words
The CMOS device of claim 1 further comprising a second voltage drop means connected in series between said second terminal and said well region, said voltage source making said well region negative with respect to ground.
Claim 6
Dependent Claim
37 words
The CMOS device of anyone of claims 1 to 3 characterized in that said voltage drop means comprises at least one PN junction diode thereby to substantially reduce the risk of latch-up of said complementary MOS device.
Claim 7
Dependent Claim
38 words
The CMOS device of claim 1 or 3 characterized in that said voltage drop means connected to said first terminal comprises: a plurality of diodes, said diodes being forward biased when power is applied to said CMOS device.
Claim 8
Dependent Claim
28 words
The CMOS device of claim 2 or 3 characterized in that said voltage drop means connected to said second terminal comprises a plurality of diodes connected in series.
Claim 9
Dependent Claim
25 words
The CMOS device of claim 6 characterized in that one or more of said diodes comprises a bipolar transistor having its collector and base interconnected.
Claim 10
Dependent Claim
26 words
The CMOS device of anyone of claims 1 to 7 characterized in that said first conductivity type is N and said second conductivity type is P.
Claim 11
Dependent Claim
38 words
The CMOS device of claim 1 combined with claim 5 characterized in that said plurality of diodes are formed in a second well region of high dopant concentration, thereby providing rather small diodes having high current handling ability.
References Cited (Backward Citations)
No citation records indexed.
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