A multiprocessor system with at least three-level memory hierarchies

Claim 2

A multiprocessor data processing system including private store in buffer caches (12, 27; 410, 424), a common shared cache (14; 412) and common main memory (4; 402), in which, while resident in cache, all shared and changed lines of data are accessible only in the common shared cache characterized in that (a) there is at least one intermediate private cache (20, 30; 418, 430) connected between main memory and each processor accessible private cache so that the size of the unit of data transfer out of main memory (call it a page) is greater than that (a line) acceptable by the processor accessible private caches or the common shared cache (b) each line in main storage is marked (WRITE FLAG, SHARE FLAG), directly or indirectly, as to whether or not it is shareable and as to whether or not it is writeable, and (c) each demanded writeable shareable line is routed exclusively to the common shared cache (14; 412), other lines being routed to private caches.

Claim 3

A system as claimed in claim 1 wherein the line marking is not generally uniform for a page (see Fig. 17), all pages being addressed to an appropriate intermediate private cache (418, 430) the shared common cache (412) being connected in parallel to the outputs of the intermediate private caches (418,430) or, where more than one intermediate private cache is chained between main memory and the processor accessible caches, in parallel to the outputs of a level of intermediate private caches at which the line marking for the unit of data transfer, between a page and a line, is uniform.

Claim 4

A system as claimed in claim 1 wherein the line marking is uniform for a page and the shared common cache is connected directly to main memory via an intermediate shared cache system (22) equivalent to the private cache systems, there being no direct data transfer provisions between the chains, main memory addressing pages to either an appropriate private or the shared cache chain.

Claim 5

A system as claimed in claim 3 wherein each page is associated with a marking field which is bit significant and specifies not only writeable and shareable potential but also in which private cache chain that page, when not both writeable and shareable, has been inserted.

Claim 6

A system as claimed in claim 4 wherein each cache is associated with its own directory mechanism (34, 38, 44, 48, 54, 60) and the cache chains interface with main memory via a storage control element (6), each processor originated line access request being processed in parallel in the shared cache chain and the appropriate private cache chain until either an effective HIT is achieved or a page demand is propogated through to the storage control element, which element responds by either addressing the page to the appropriate cache chain in dependence on the states of the associated marking field or generating a system interrupt if the request is not compatible with the bit states in the associated marking field, a non-effective intermediate HIT also generating a system interrupt.

Claim 7

In a multiprocessor system, including a three level memory hierarchy, the combination comprising: at least first and second processors; a main memory at memory level three, in which a plurality of pieces of information, which each include WRITE and SHARE flags, are stored at addressable locations; at least first and second private caches at memory level two, which are operative with said at least first and second processors respectively in which a given number of pieces of information previously transferred from main memory are stored; a first shared cache at memory level two, which is operative with each of said at least first and second processors, in which a given number of pieces of information previously transferred from main memory are stored; at least third and fourth private caches at memory level one, which are operative with said at least first and second private caches, respectively, and said at least first and second processors, respectively, in which a given number of pieces of information previously transferred from said at least first and second private caches, respectively are stored; a second shared cache at memory level one, which is operative with said first shared cache and each of said at least first and second processors, in which a given number of pieces of information previously transferred from said first shared cache are stored; and a system control element which is operative with said main memory at memory'level three and said at least first and second private caches and said first shared cache at memory level two, and which is operative in response to a given processor interrogating its associated private caches and shared caches at memory levels one and two to access a selected piece of information which is found to be not stored therein, with said system control element checking the state of said WRITE and SHARE flags of said selected piece of information in said main memory, for transferring said selected piece of information to said first shared cache at memory level two when said WRITE and SHARE flags are each in a predetermined state, and for transferring said selected piece of information to one of said first and second private caches at memory level two when said WRITE and SHARE flags are not each in said predetermined state.

Claim 8

In a multiprocessor system, including a three level memory hierarchy, the combination comprising: at least first and second processors; a main memory at memory level three, in which a plurality of pieces of information, which each include WRITE and SHARE flags, are stored at addressable locations; at least first and second private caches at memory level two, which are operative with said at least first and second processors respectively in which a given number of pieces of information previously transferred from main memory are stored; a first shared cache at memory level two, which is operative with each of said at least first and second processors, in which a given number of pieces of information previously transferred from main memory are stored; at least third and fourth private caches at memory level one, which are operative with said at least first and second private caches, respectively, and said at least first and second processors, respectively, in which a given number of pieces of information previously transferred from said at least first and second private caches, respectively are stored; a second shared cache at memory level one, which is operative with said first shared cache and each of said at least first and second processors, in which a given number of pieces of information previously transferred from said first shared cache are stored; and a system control element which is operative with said main memory at memory'level three and said at least first and second private caches and said first shared cache at memory level two, and which is operative in response to a given processor interrogating its associated private caches and shared caches at memory levels one and two to access a selected piece of information which is found to be not stored therein, with said system control element checking the state of said WRITE and SHARE flags of said selected piece of information in said main memory, for transferring said selected piece of information to said first shared cache at memory level two when said WRITE and SHARE flags are each in a predetermined state, and for transferring said selected piece of information to one of said first and second private caches at memory level two when said WRITE and SHARE flags are not each in said predetermined state.

Claim 9

In a multiprocessor system, including a three level memory hierarchy, the combination comprising: at least first and second processors; a main memory at memory level three, in which a plurality of pieces of information, which each include WRITE and SHARE flags, are stored at addressable locations; at least first and second private caches at memory level two, which are operative with said at least first and second processors respectively, in which a given number of pieces of information previously transferred from main memory are stored; at least third and fourth private caches at memory level one, which are operative with said at least first and second private caches, respectively, and said at least first and second processors, respectively, in which a given number of pieces of information previously transferred from said at least first and second private caches, respectively are stored; a shared cache, which is operative with each of said at least first and second processor, in which a given number of pieces of information previously transferred from said at least first and second private caches are stored; a system control element which is operative with said main memory at memory level three and said at least first and second private caches at memory level two, and which is operative in response to a given processor interrogating its associated private caches at memory levels one and two and said shared cache to access a selected piece of information which is found to be not stored therein, with said system control element transferring said selected piece of information to the private cache at memory level two, which is associated with said given processor; and means included in the private cache at memory level two which is associated with said given processor for transferring said selected piece of information to said shared cache when said WRITE and SHARE flags are in a predetermined state, and for transferring said selected piece of information to one of said first and second private caches at memory level one when said WRITE and SHARE flags are not in said predetermined state.

Claim 10

In a multiprocessor system, including a three level memory hierarchy, the combination comprising: at least first and second processors; a main memory at memory level three, in which a plurality of pieces of information, which each include WRITE and SHARE flags, are stored at addressable locations; at least first and second private caches at memory level two, which are operative with said at least first and second processors respectively, in which a given number of pieces of information previously transferred from main memory are stored; at least third and fourth private caches at memory level one, which are operative with said at least first and second private caches, respectively, and said at least first and second processors, respectively, in which a given number of pieces of information previously transferred from said at least first and second private caches, respectively are stored; a shared cache, which is operative with each of said at least first and second processor, in which a given number of pieces of information previously transferred from said at least first and second private caches are stored; a system control element which is operative with said main memory at memory level three and said at least first and second private caches at memory level two, and which is operative in response to a given processor interrogating its associated private caches at memory levels one and two and said shared cache to access a selected piece of information which is found to be not stored therein, with said system control element transferring said selected piece of information to the private cache at memory level two, which is associated with said given processor; and means included in the private cache at memory level two which is associated with said given processor for transferring said selected piece of information to said shared cache when said WRITE and SHARE flags are in a predetermined state, and for transferring said selected piece of information to one of said first and second private caches at memory level one when said WRITE and SHARE flags are not in said predetermined state.

Claim 11

A system as claimed in claim 5 in which further processors, as a group or as more than one group, share main memory, but use their own cache systems, the hierarchy effectively branching at the storage control element.